| Message ID | 1450780234-17236-7-git-send-email-huaitong.han@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 22.12.15 at 11:30, <huaitong.han@intel.com> wrote: > This patch adds pkeys support for cpuid handing. > > Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is > CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE. > > Signed-off-by: Huaitong Han <huaitong.han@intel.com> > --- > tools/libxc/xc_cpufeature.h | 2 ++ > tools/libxc/xc_cpuid_x86.c | 6 ++++-- > xen/arch/x86/hvm/hvm.c | 36 +++++++++++++++++++++++------------- > 3 files changed, 29 insertions(+), 15 deletions(-) > > diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h > index c3ddc80..f6a9778 100644 > --- a/tools/libxc/xc_cpufeature.h > +++ b/tools/libxc/xc_cpufeature.h > @@ -141,5 +141,7 @@ > #define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */ > #define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */ > > +/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx) */ > +#define X86_FEATURE_PKU 3 > > #endif /* __LIBXC_CPUFEATURE_H */ > diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c > index 8882c01..1ce979b 100644 > --- a/tools/libxc/xc_cpuid_x86.c > +++ b/tools/libxc/xc_cpuid_x86.c > @@ -427,9 +427,11 @@ static void xc_cpuid_hvm_policy(xc_interface *xch, > bitmaskof(X86_FEATURE_ADX) | > bitmaskof(X86_FEATURE_SMAP) | > bitmaskof(X86_FEATURE_FSGSBASE)); > + regs[2] &= bitmaskof(X86_FEATURE_PKU); > } else > - regs[1] = 0; > - regs[0] = regs[2] = regs[3] = 0; > + regs[1] = regs[2] = 0; > + > + regs[0] = regs[3] = 0; > break; > > case 0x0000000d: > diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c > index 59916ed..076313b 100644 > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -4572,7 +4572,7 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, > unsigned int *ebx, > __clear_bit(X86_FEATURE_APIC & 31, edx); > > /* Fix up OSXSAVE. */ > - if ( cpu_has_xsave ) > + if ( *ecx & cpufeat_mask(X86_FEATURE_XSAVE) ) > *ecx |= (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_OSXSAVE) ? > cpufeat_mask(X86_FEATURE_OSXSAVE) : 0; > > @@ -4585,21 +4585,31 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, > unsigned int *ebx, > *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); > break; > case 0x7: > - if ( (count == 0) && !cpu_has_smep ) > - *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP); > + if ( count == 0 ) > + { > + if ( !cpu_has_smep ) > + *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP); > > - if ( (count == 0) && !cpu_has_smap ) > - *ebx &= ~cpufeat_mask(X86_FEATURE_SMAP); > + if ( !cpu_has_smap ) > + *ebx &= ~cpufeat_mask(X86_FEATURE_SMAP); > > - /* Don't expose MPX to hvm when VMX support is not available */ > - if ( (count == 0) && > - (!(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || > - !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS)) ) > - *ebx &= ~cpufeat_mask(X86_FEATURE_MPX); > + /* Don't expose MPX to hvm when VMX support is not available */ Please fix the comment style if you touch this anyway. > + if (!(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || > + !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS)) > + *ebx &= ~cpufeat_mask(X86_FEATURE_MPX); > > - /* Don't expose INVPCID to non-hap hvm. */ > - if ( (count == 0) && !hap_enabled(d) ) > - *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); > + if ( !hap_enabled(d) ) > + { > + /* Don't expose INVPCID to non-hap hvm. */ > + *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); > + /* X86_FEATURE_PKU is not yet implemented for shadow paging. */ > + *ecx &= ~cpufeat_mask(X86_FEATURE_PKU); > + } > + > + if ( *ecx & cpufeat_mask(X86_FEATURE_PKU)) > + *ecx |= (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PKE) ? > + cpufeat_mask(X86_FEATURE_OSPKE) : 0; Bogus use of ?: considering that you or in zero in its "false" case. Just extend the if() condition. Jan
diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h index c3ddc80..f6a9778 100644 --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -141,5 +141,7 @@ #define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */ +/* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx) */ +#define X86_FEATURE_PKU 3 #endif /* __LIBXC_CPUFEATURE_H */ diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index 8882c01..1ce979b 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -427,9 +427,11 @@ static void xc_cpuid_hvm_policy(xc_interface *xch, bitmaskof(X86_FEATURE_ADX) | bitmaskof(X86_FEATURE_SMAP) | bitmaskof(X86_FEATURE_FSGSBASE)); + regs[2] &= bitmaskof(X86_FEATURE_PKU); } else - regs[1] = 0; - regs[0] = regs[2] = regs[3] = 0; + regs[1] = regs[2] = 0; + + regs[0] = regs[3] = 0; break; case 0x0000000d: diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 59916ed..076313b 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4572,7 +4572,7 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, __clear_bit(X86_FEATURE_APIC & 31, edx); /* Fix up OSXSAVE. */ - if ( cpu_has_xsave ) + if ( *ecx & cpufeat_mask(X86_FEATURE_XSAVE) ) *ecx |= (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_OSXSAVE) ? cpufeat_mask(X86_FEATURE_OSXSAVE) : 0; @@ -4585,21 +4585,31 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); break; case 0x7: - if ( (count == 0) && !cpu_has_smep ) - *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP); + if ( count == 0 ) + { + if ( !cpu_has_smep ) + *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP); - if ( (count == 0) && !cpu_has_smap ) - *ebx &= ~cpufeat_mask(X86_FEATURE_SMAP); + if ( !cpu_has_smap ) + *ebx &= ~cpufeat_mask(X86_FEATURE_SMAP); - /* Don't expose MPX to hvm when VMX support is not available */ - if ( (count == 0) && - (!(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || - !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS)) ) - *ebx &= ~cpufeat_mask(X86_FEATURE_MPX); + /* Don't expose MPX to hvm when VMX support is not available */ + if (!(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || + !(vmx_vmentry_control & VM_ENTRY_LOAD_BNDCFGS)) + *ebx &= ~cpufeat_mask(X86_FEATURE_MPX); - /* Don't expose INVPCID to non-hap hvm. */ - if ( (count == 0) && !hap_enabled(d) ) - *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); + if ( !hap_enabled(d) ) + { + /* Don't expose INVPCID to non-hap hvm. */ + *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); + /* X86_FEATURE_PKU is not yet implemented for shadow paging. */ + *ecx &= ~cpufeat_mask(X86_FEATURE_PKU); + } + + if ( *ecx & cpufeat_mask(X86_FEATURE_PKU)) + *ecx |= (v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PKE) ? + cpufeat_mask(X86_FEATURE_OSPKE) : 0; + } break; case 0xb: /* Fix the x2APIC identifier. */
This patch adds pkeys support for cpuid handing. Pkeys hardware support is CPUID.7.0.ECX[3]:PKU. software support is CPUID.7.0.ECX[4]:OSPKE and it reflects the support setting of CR4.PKE. Signed-off-by: Huaitong Han <huaitong.han@intel.com> --- tools/libxc/xc_cpufeature.h | 2 ++ tools/libxc/xc_cpuid_x86.c | 6 ++++-- xen/arch/x86/hvm/hvm.c | 36 +++++++++++++++++++++++------------- 3 files changed, 29 insertions(+), 15 deletions(-)