From patchwork Sat Jan 23 09:20:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 8096261 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B9A88BEEE5 for ; Sat, 23 Jan 2016 09:25:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A19AF205B1 for ; Sat, 23 Jan 2016 09:25:53 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 950EE205B5 for ; Sat, 23 Jan 2016 09:25:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aMuPG-0007dx-5m; Sat, 23 Jan 2016 09:22:54 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aMuPD-0007cr-No for xen-devel@lists.xen.org; Sat, 23 Jan 2016 09:22:51 +0000 Received: from [85.158.139.211] by server-5.bemta-5.messagelabs.com id 83/4F-03225-B6643A65; Sat, 23 Jan 2016 09:22:51 +0000 X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-9.tower-206.messagelabs.com!1453540964!17686231!1 X-Originating-IP: [119.145.14.65] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NSA9PiA3NzQ2Mw==\n X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 49861 invoked from network); 23 Jan 2016 09:22:49 -0000 Received: from szxga02-in.huawei.com (HELO szxga02-in.huawei.com) (119.145.14.65) by server-9.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 23 Jan 2016 09:22:49 -0000 Received: from 172.24.1.47 (EHLO szxeml427-hub.china.huawei.com) ([172.24.1.47]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAK81953; Sat, 23 Jan 2016 17:22:25 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml427-hub.china.huawei.com (10.82.67.182) with Microsoft SMTP Server id 14.3.235.1; Sat, 23 Jan 2016 17:22:16 +0800 From: Shannon Zhao To: Date: Sat, 23 Jan 2016 17:20:00 +0800 Message-ID: <1453540813-15764-9-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1453540813-15764-1-git-send-email-zhaoshenglong@huawei.com> References: <1453540813-15764-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.56A34651.003E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fca5855d53824346bd434bc70c6f81cc Cc: ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com, peter.huangpeng@huawei.com, julien.grall@citrix.com, stefano.stabellini@citrix.com, shannon.zhao@linaro.org, Jan Beulich Subject: [Xen-devel] [PATCH v4 08/21] arm/acpi: Parse MADT to map logical cpu to MPIDR and get cpu_possible_map X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Parth Dixit MADT contains the information for MPIDR which is essential for SMP initialization, parse the GIC cpu interface structures to get the MPIDR value and map it to cpu_logical_map(), and add enabled cpu with valid MPIDR into cpu_possible_map. Move BAD_MADT_ENTRY to common place. Cc: Jan Beulich Signed-off-by: Hanjun Guo Signed-off-by: Tomasz Nowicki Signed-off-by: Naresh Bhat Signed-off-by: Parth Dixit Signed-off-by: Shannon Zhao --- V4: fix coding style and address some comments --- xen/arch/arm/acpi/boot.c | 129 +++++++++++++++++++++++++++++++++++++++++++++ xen/arch/x86/acpi/boot.c | 4 -- xen/include/asm-arm/acpi.h | 2 + xen/include/xen/acpi.h | 4 ++ 4 files changed, 135 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/acpi/boot.c b/xen/arch/arm/acpi/boot.c index 6b33fbe..c9135f2 100644 --- a/xen/arch/arm/acpi/boot.c +++ b/xen/arch/arm/acpi/boot.c @@ -32,6 +32,135 @@ #include #include +#include + +/* Processors with enabled flag and sane MPIDR */ +static unsigned int enabled_cpus; + +/* Boot CPU is valid or not in MADT */ +static bool_t __initdata bootcpu_valid; + +/* total number of cpus in this system */ +static unsigned int __initdata total_cpus; + +/* + * acpi_map_gic_cpu_interface - generates a logical cpu number + * and map to MPIDR represented by GICC structure + */ +static void __init +acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) +{ + int i; + u64 mpidr = processor->arm_mpidr & MPIDR_HWID_MASK; + bool_t enabled = !!(processor->flags & ACPI_MADT_ENABLED); + + if ( mpidr == MPIDR_INVALID ) + { + printk("Skip MADT cpu entry with invalid MPIDR\n"); + return; + } + + total_cpus++; + if ( !enabled ) + return; + + if ( enabled_cpus >= NR_CPUS ) + { + printk("NR_CPUS limit of %d reached, Processor %d/0x%"PRIx64" ignored.\n", + NR_CPUS, total_cpus, mpidr); + return; + } + + /* Check if GICC structure of boot CPU is available in the MADT */ + if ( cpu_logical_map(0) == mpidr ) + { + if ( bootcpu_valid ) + { + printk("Firmware bug, duplicate CPU MPIDR: 0x%"PRIx64" in MADT\n", + mpidr); + return; + } + + bootcpu_valid = true; + } + + /* + * Duplicate MPIDRs are a recipe for disaster. Scan + * all initialized entries and check for + * duplicates. If any is found just ignore the CPU. + */ + for ( i = 1; i < enabled_cpus; i++ ) + { + if ( cpu_logical_map(i) == mpidr ) + { + printk("Firmware bug, duplicate CPU MPIDR: 0x%"PRIx64" in MADT\n", + mpidr); + return; + } + } + + if ( !acpi_psci_present() ) + return; + + /* CPU 0 was already initialized */ + if ( enabled_cpus ) + { + if ( arch_cpu_init(enabled_cpus, NULL) < 0 ) + return; + + /* map the logical cpu id to cpu MPIDR */ + cpu_logical_map(enabled_cpus) = mpidr; + } + + enabled_cpus++; +} + +static int __init +acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_interrupt *processor = + container_of(header, struct acpi_madt_generic_interrupt, header); + + if ( BAD_MADT_ENTRY(processor, end) ) + return -EINVAL; + + acpi_table_print_madt_entry(header); + acpi_map_gic_cpu_interface(processor); + return 0; +} + +/* Parse GIC cpu interface entries in MADT for SMP init */ +void __init acpi_smp_init_cpus(void) +{ + int count, i; + + /* + * do a partial walk of MADT to determine how many CPUs + * we have including disabled CPUs, and get information + * we need for SMP init + */ + count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, + acpi_parse_gic_cpu_interface, 0); + + if ( count <= 0 ) + { + printk("Error parsing GIC CPU interface entry\n"); + return; + } + + if ( !bootcpu_valid ) + { + printk("MADT missing boot CPU MPIDR, not enabling secondaries\n"); + return; + } + + for ( i = 0; i < enabled_cpus; i++ ) + cpumask_set_cpu(i, &cpu_possible_map); + + /* Make boot-up look pretty */ + printk("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus); +} static int __init acpi_parse_fadt(struct acpi_table_header *table) { diff --git a/xen/arch/x86/acpi/boot.c b/xen/arch/x86/acpi/boot.c index fac36c6..385c0be 100644 --- a/xen/arch/x86/acpi/boot.c +++ b/xen/arch/x86/acpi/boot.c @@ -43,10 +43,6 @@ #include #include -#define BAD_MADT_ENTRY(entry, end) ( \ - (!entry) || (unsigned long)entry + sizeof(*entry) > end || \ - ((struct acpi_subtable_header *)entry)->length != sizeof(*entry)) - #define PREFIX "ACPI: " bool_t __initdata acpi_noirq; /* skip ACPI IRQ initialization */ diff --git a/xen/include/asm-arm/acpi.h b/xen/include/asm-arm/acpi.h index 1ce88f8..89d17e8 100644 --- a/xen/include/asm-arm/acpi.h +++ b/xen/include/asm-arm/acpi.h @@ -35,9 +35,11 @@ extern bool_t acpi_disabled; #ifdef CONFIG_ACPI bool_t __init acpi_psci_present(void); bool_t __init acpi_psci_hvc_present(void); +void __init acpi_smp_init_cpus(void); #else static inline bool_t acpi_psci_present(void) { return false; } static inline bool_t acpi_psci_hvc_present(void) {return false; } +static inline void acpi_smp_init_cpus(void) { } #endif /* CONFIG_ACPI */ /* Basic configuration for ACPI */ diff --git a/xen/include/xen/acpi.h b/xen/include/xen/acpi.h index 65e53a6..bc73310 100644 --- a/xen/include/xen/acpi.h +++ b/xen/include/xen/acpi.h @@ -39,6 +39,10 @@ #define ACPI_MADT_GET_POLARITY(inti) ACPI_MADT_GET_(POLARITY, inti) #define ACPI_MADT_GET_TRIGGER(inti) ACPI_MADT_GET_(TRIGGER, inti) +#define BAD_MADT_ENTRY(entry, end) ( \ + (!entry) || (unsigned long)entry + sizeof(*entry) > end || \ + ((struct acpi_subtable_header *)entry)->length < sizeof(*entry)) + #ifdef CONFIG_ACPI_BOOT enum acpi_interrupt_id {