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BN3PR0701MB1688; 5:1zAen+SKQTVcsiiiVrrmwOCAsdOaGnY9mVZKa+4JLbmOB7YFP3K9DOcgCnHK2Km8VfQdYoHSm02dHMdGO5/4zH4QFzN/S00uf/PUyl9HBpwgfIByTecR1hMDGvKisjkMuOpQxi7vfSvPSxgg/epfvA==; 24:SNqzSa5XXCud4xuCfHZX5CGGcjvRX44JVoXlKESBoibxYGSvtZ0HlXhajv58xM+lcMYIvPUcmSuzdVyGvVskFJoldnaUW/6O02q7lEo32vo= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2016 09:28:46.5461 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR0701MB1688 X-Mailman-Approved-At: Mon, 01 Feb 2016 09:30:20 +0000 Cc: Prasun.Kapoor@caviumnetworks.com, manish.jaggi@caviumnetworks.com, Vijaya Kumar K , vijay.kilari@gmail.com Subject: [Xen-devel] [PATCH v8 13/28] xen/arm: Correct GICD_TYPER register definition typos X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vijaya Kumar K GICD_TYPER register definitions are defined as GICD_TYPE. Rename all GICD_TYPE_* as GICD_TYPER_* Signed-off-by: Vijaya Kumar K --- xen/arch/arm/gic-hip04.c | 4 ++-- xen/arch/arm/gic-v2.c | 6 +++--- xen/arch/arm/gic-v3.c | 2 +- xen/arch/arm/vgic-v2.c | 2 +- xen/arch/arm/vgic-v3.c | 4 ++-- xen/include/asm-arm/gic.h | 8 ++++---- xen/include/asm-arm/gic_v3_defs.h | 2 +- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c index 193849e..aa57587 100644 --- a/xen/arch/arm/gic-hip04.c +++ b/xen/arch/arm/gic-hip04.c @@ -274,11 +274,11 @@ static void __init hip04gic_dist_init(void) writel_gicd(0, GICD_CTLR); type = readl_gicd(GICD_TYPER); - nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); + nr_lines = 32 * ((type & GICD_TYPER_LINES) + 1); gic_cpus = 16; printk("GIC-HIP04: %d lines, %d cpu%s%s (IID %8.8x).\n", nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s", - (type & GICD_TYPE_SEC) ? ", secure" : "", + (type & GICD_TYPER_SEC) ? ", secure" : "", readl_gicd(GICD_IIDR)); /* Default all global IRQs to level, active low */ diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index d8de68e..daa5a76 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -260,11 +260,11 @@ static void __init gicv2_dist_init(void) writel_gicd(0, GICD_CTLR); type = readl_gicd(GICD_TYPER); - nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); - gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5); + nr_lines = 32 * ((type & GICD_TYPER_LINES) + 1); + gic_cpus = 1 + ((type & GICD_TYPER_CPUS) >> 5); printk("GICv2: %d lines, %d cpu%s%s (IID %8.8x).\n", nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s", - (type & GICD_TYPE_SEC) ? ", secure" : "", + (type & GICD_TYPER_SEC) ? ", secure" : "", readl_gicd(GICD_IIDR)); /* Default all global IRQs to level, active low */ diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 45fe624..0e1e2f8 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -574,7 +574,7 @@ static void __init gicv3_dist_init(void) writel_relaxed(0, GICD + GICD_CTLR); type = readl_relaxed(GICD + GICD_TYPER); - nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); + nr_lines = 32 * ((type & GICD_TYPER_LINES) + 1); printk("GICv3: %d lines, (IID %8.8x).\n", nr_lines, readl_relaxed(GICD + GICD_IIDR)); diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 9adb4a9..1f6619d 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -192,7 +192,7 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info, if ( dabt.size != DABT_WORD ) goto bad_width; /* No secure world support for guests. */ vgic_lock(v); - typer = ((v->domain->max_vcpus - 1) << GICD_TYPE_CPUS_SHIFT) + typer = ( ((v->domain->max_vcpus - 1) << GICD_TYPER_CPUS_SHIFT) ) | DIV_ROUND_UP(v->domain->arch.vgic.nr_spis, 32); vgic_unlock(v); diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 70cf67e..d9b8539 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -919,10 +919,10 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info, if ( dabt.size != DABT_WORD ) goto bad_width; /* No secure world support for guests. */ - typer = ((ncpus - 1) << GICD_TYPE_CPUS_SHIFT | + typer = ((ncpus - 1) << GICD_TYPER_CPUS_SHIFT | DIV_ROUND_UP(v->domain->arch.vgic.nr_spis, 32)); - typer |= (irq_bits - 1) << GICD_TYPE_ID_BITS_SHIFT; + typer |= (irq_bits - 1) << GICD_TYPER_ID_BITS_SHIFT; *r = vgic_reg32_extract(typer, info); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 6b4883a..bdcb189 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -98,10 +98,10 @@ /* Register bits */ #define GICD_CTL_ENABLE 0x1 -#define GICD_TYPE_LINES 0x01f -#define GICD_TYPE_CPUS_SHIFT 5 -#define GICD_TYPE_CPUS 0x0e0 -#define GICD_TYPE_SEC 0x400 +#define GICD_TYPER_LINES 0x01f +#define GICD_TYPER_CPUS_SHIFT 5 +#define GICD_TYPER_CPUS 0x0e0 +#define GICD_TYPER_SEC 0x400 #define GICC_CTL_ENABLE 0x1 #define GICC_CTL_EOI (0x1 << 9) diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index f02e1aae..50d2056 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -44,7 +44,7 @@ #define GICC_SRE_EL2_ENEL1 (1UL << 3) /* Additional bits in GICD_TYPER defined by GICv3 */ -#define GICD_TYPE_ID_BITS_SHIFT 19 +#define GICD_TYPER_ID_BITS_SHIFT (19) #define GICD_TYPER_LPIS_SUPPORTED (1U << 17) #define GICD_CTLR_RWP (1UL << 31)