From patchwork Tue Feb 2 07:11:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shuai Ruan X-Patchwork-Id: 8187241 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A6C4CBEEE5 for ; Tue, 2 Feb 2016 07:16:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BC62E20253 for ; Tue, 2 Feb 2016 07:16:01 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [50.57.142.19]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DDECB20254 for ; Tue, 2 Feb 2016 07:16:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aQV9K-0006E4-M9; Tue, 02 Feb 2016 07:13:18 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1aQV9I-0006Ds-Pa for xen-devel@lists.xen.org; Tue, 02 Feb 2016 07:13:16 +0000 Received: from [85.158.137.68] by server-16.bemta-3.messagelabs.com id 22/53-07451-B0750B65; Tue, 02 Feb 2016 07:13:15 +0000 X-Env-Sender: shuai.ruan@linux.intel.com X-Msg-Ref: server-15.tower-31.messagelabs.com!1454397192!19344613!3 X-Originating-IP: [134.134.136.24] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjQgPT4gMzkwOTcx\n X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10190 invoked from network); 2 Feb 2016 07:13:15 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by server-15.tower-31.messagelabs.com with SMTP; 2 Feb 2016 07:13:15 -0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 01 Feb 2016 23:13:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,384,1449561600"; d="scan'208";a="894419512" Received: from rs-vmm.bj.intel.com ([10.238.135.71]) by fmsmga001.fm.intel.com with ESMTP; 01 Feb 2016 23:13:14 -0800 From: Shuai Ruan To: xen-devel@lists.xen.org Date: Tue, 2 Feb 2016 15:11:04 +0800 Message-Id: <1454397064-29268-3-git-send-email-shuai.ruan@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454397064-29268-1-git-send-email-shuai.ruan@linux.intel.com> References: <1454397064-29268-1-git-send-email-shuai.ruan@linux.intel.com> Cc: andrew.cooper3@citrix.com, keir@xen.org, jbeulich@suse.com Subject: [Xen-devel] [PATCH 2/2] x86/xsave: use alternative asm on xsave side. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch use alternavtive asm on the xsave side. As xsaves use modified optimization like xsaveopt, xsaves may not writing the FPU portion of the save image too. So xsaves also need some extra tweaks. Signed-off-by: Shuai Ruan Reviewed-by: Jan Beulich --- xen/arch/x86/xstate.c | 49 ++++++++++++++++--------------------------------- 1 file changed, 16 insertions(+), 33 deletions(-) diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 4e87ab3..832f4ad 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -248,24 +248,26 @@ void xsave(struct vcpu *v, uint64_t mask) uint32_t hmask = mask >> 32; uint32_t lmask = mask; int word_size = mask & XSTATE_FP ? (cpu_has_fpu_sel ? 8 : 0) : -1; +#define XSAVE(pfx) \ + alternative_io_3(".byte " pfx "0x0f,0xae,0x27\n", \ + ".byte " pfx "0x0f,0xae,0x37\n", \ + X86_FEATURE_XSAVEOPT, \ + ".byte " pfx "0x0f,0xc7,0x27\n", \ + X86_FEATURE_XSAVEC, \ + ".byte " pfx "0x0f,0xc7,0x37\n", \ + X86_FEATURE_XSAVES, \ + "=m" (*ptr), \ + "a" (lmask), "d" (hmask), "D" (ptr)) if ( word_size <= 0 || !is_pv_32bit_vcpu(v) ) { typeof(ptr->fpu_sse.fip.sel) fcs = ptr->fpu_sse.fip.sel; typeof(ptr->fpu_sse.fdp.sel) fds = ptr->fpu_sse.fdp.sel; - if ( cpu_has_xsaves ) - asm volatile ( ".byte 0x48,0x0f,0xc7,0x2f" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); - else if ( cpu_has_xsavec ) - asm volatile ( ".byte 0x48,0x0f,0xc7,0x27" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); - else if ( cpu_has_xsaveopt ) + if ( cpu_has_xsaveopt || cpu_has_xsaves ) { /* - * xsaveopt may not write the FPU portion even when the respective + * xsaveopt/xsaves may not write the FPU portion even when the respective * mask bit is set. For the check further down to work we hence * need to put the save image back into the state that it was in * right after the previous xsaveopt. @@ -277,14 +279,9 @@ void xsave(struct vcpu *v, uint64_t mask) ptr->fpu_sse.fip.sel = 0; ptr->fpu_sse.fdp.sel = 0; } - asm volatile ( ".byte 0x48,0x0f,0xae,0x37" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); } - else - asm volatile ( ".byte 0x48,0x0f,0xae,0x27" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); + + XSAVE("0x48,"); if ( !(mask & ptr->xsave_hdr.xstate_bv & XSTATE_FP) || /* @@ -315,24 +312,10 @@ void xsave(struct vcpu *v, uint64_t mask) } else { - if ( cpu_has_xsaves ) - asm volatile ( ".byte 0x0f,0xc7,0x2f" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); - else if ( cpu_has_xsavec ) - asm volatile ( ".byte 0x0f,0xc7,0x27" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); - else if ( cpu_has_xsaveopt ) - asm volatile ( ".byte 0x0f,0xae,0x37" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); - else - asm volatile ( ".byte 0x0f,0xae,0x27" - : "=m" (*ptr) - : "a" (lmask), "d" (hmask), "D" (ptr) ); + XSAVE(""); word_size = 4; } +#undef XSAVE if ( word_size >= 0 ) ptr->fpu_sse.x[FPU_WORD_SIZE_OFFSET] = word_size; }