From patchwork Sun Feb 28 12:54:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 8446221 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B78799F2F0 for ; Sun, 28 Feb 2016 12:59:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9EC6E20340 for ; Sun, 28 Feb 2016 12:59:42 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8453F20320 for ; Sun, 28 Feb 2016 12:59:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aa0u4-00064K-Qr; Sun, 28 Feb 2016 12:56:52 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1aa0u3-00063n-PO for xen-devel@lists.xen.org; Sun, 28 Feb 2016 12:56:51 +0000 Received: from [85.158.137.68] by server-15.bemta-3.messagelabs.com id 7E/4F-03172-29EE2D65; Sun, 28 Feb 2016 12:56:50 +0000 X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-8.tower-31.messagelabs.com!1456664209!25675675!1 X-Originating-IP: [134.134.136.24] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjQgPT4gMzkwOTcx\n X-StarScan-Received: X-StarScan-Version: 7.35.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 27427 invoked from network); 28 Feb 2016 12:56:49 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by server-8.tower-31.messagelabs.com with SMTP; 28 Feb 2016 12:56:49 -0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 28 Feb 2016 04:56:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,514,1449561600"; d="scan'208";a="912872358" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.13.126]) by fmsmga001.fm.intel.com with ESMTP; 28 Feb 2016 04:56:47 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Sun, 28 Feb 2016 20:54:53 +0800 Message-Id: <1456664094-5161-5-git-send-email-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.4.8 In-Reply-To: <1456664094-5161-1-git-send-email-haozhong.zhang@intel.com> References: <1456664094-5161-1-git-send-email-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Kevin Tian , Keir Fraser , Jan Beulich , Andrew Cooper , Jun Nakajima Subject: [Xen-devel] [PATCH v6 4/5] vmx: Add VMX RDTSC(P) scaling support X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the initialization and setup code for VMX TSC scaling. Signed-off-by: Haozhong Zhang Acked-by: Jan Beulich Acked-by: Kevin Tian --- CC: Keir Fraser CC: Jan Beulich CC: Andrew Cooper CC: Jun Nakajima CC: Kevin Tian --- Changes in v6: * Adapt to the macro renaming in patch 1. * No functionality changes. --- xen/arch/x86/hvm/hvm.c | 6 ++++++ xen/arch/x86/hvm/vmx/vmcs.c | 12 +++++++++--- xen/arch/x86/hvm/vmx/vmx.c | 17 +++++++++++++++++ xen/include/asm-x86/hvm/hvm.h | 3 +++ xen/include/asm-x86/hvm/vmx/vmcs.h | 7 +++++++ 5 files changed, 42 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 50e5a5c..9059bbc 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2123,6 +2123,9 @@ static int hvm_load_cpu_ctxt(struct domain *d, hvm_domain_context_t *h) if ( hvm_funcs.load_cpu_ctxt(v, &ctxt) < 0 ) return -EINVAL; + if ( hvm_funcs.tsc_scaling.setup ) + hvm_funcs.tsc_scaling.setup(v); + v->arch.hvm_vcpu.msr_tsc_aux = ctxt.msr_tsc_aux; hvm_set_guest_tsc_fixed(v, ctxt.tsc, d->arch.hvm_domain.sync_tsc); @@ -5638,6 +5641,9 @@ void hvm_vcpu_reset_state(struct vcpu *v, uint16_t cs, uint16_t ip) hvm_set_segment_register(v, x86_seg_gdtr, ®); hvm_set_segment_register(v, x86_seg_idtr, ®); + if ( hvm_funcs.tsc_scaling.setup ) + hvm_funcs.tsc_scaling.setup(v); + /* Sync AP's TSC with BSP's. */ v->arch.hvm_vcpu.cache_tsc_offset = v->domain->vcpu[0]->arch.hvm_vcpu.cache_tsc_offset; diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 5bc3c74..d506f80 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -149,6 +149,7 @@ static void __init vmx_display_features(void) P(cpu_has_vmx_vmfunc, "VM Functions"); P(cpu_has_vmx_virt_exceptions, "Virtualisation Exceptions"); P(cpu_has_vmx_pml, "Page Modification Logging"); + P(cpu_has_vmx_tsc_scaling, "TSC Scaling"); #undef P if ( !printed ) @@ -243,7 +244,8 @@ static int vmx_init_vmcs_config(void) SECONDARY_EXEC_ENABLE_VM_FUNCTIONS | SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS | SECONDARY_EXEC_XSAVES | - SECONDARY_EXEC_PCOMMIT); + SECONDARY_EXEC_PCOMMIT | + SECONDARY_EXEC_TSC_SCALING); rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); if ( _vmx_misc_cap & VMX_MISC_VMWRITE_ALL ) opt |= SECONDARY_EXEC_ENABLE_VMCS_SHADOWING; @@ -1000,7 +1002,7 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_control); v->arch.hvm_vmx.exec_control = vmx_cpu_based_exec_control; - if ( d->arch.vtsc ) + if ( d->arch.vtsc && !cpu_has_vmx_tsc_scaling ) v->arch.hvm_vmx.exec_control |= CPU_BASED_RDTSC_EXITING; v->arch.hvm_vmx.secondary_exec_control = vmx_secondary_exec_control; @@ -1288,6 +1290,9 @@ static int construct_vmcs(struct vcpu *v) if ( cpu_has_vmx_xsaves ) __vmwrite(XSS_EXIT_BITMAP, 0); + if ( cpu_has_vmx_tsc_scaling ) + __vmwrite(TSC_MULTIPLIER, d->arch.hvm_domain.tsc_scaling_ratio); + vmx_vmcs_exit(v); /* PVH: paging mode is updated by arch_set_info_guest(). */ @@ -1870,7 +1875,8 @@ void vmcs_dump_vcpu(struct vcpu *v) vmr32(VM_EXIT_REASON), vmr(EXIT_QUALIFICATION)); printk("IDTVectoring: info=%08x errcode=%08x\n", vmr32(IDT_VECTORING_INFO), vmr32(IDT_VECTORING_ERROR_CODE)); - printk("TSC Offset = 0x%016lx\n", vmr(TSC_OFFSET)); + printk("TSC Offset = 0x%016lx TSC Multiplier = 0x%016lx\n", + vmr(TSC_OFFSET), vmr(TSC_MULTIPLIER)); if ( (v->arch.hvm_vmx.exec_control & CPU_BASED_TPR_SHADOW) || (vmx_pin_based_exec_control & PIN_BASED_POSTED_INTERRUPT) ) printk("TPR Threshold = 0x%02x PostedIntrVec = 0x%02x\n", diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index b949d9c..a201b74 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1122,6 +1122,16 @@ static void vmx_handle_cd(struct vcpu *v, unsigned long value) } } +static void vmx_setup_tsc_scaling(struct vcpu *v) +{ + if ( !hvm_tsc_scaling_supported || v->domain->arch.vtsc ) + return; + + vmx_vmcs_enter(v); + __vmwrite(TSC_MULTIPLIER, hvm_tsc_scaling_ratio(v->domain)); + vmx_vmcs_exit(v); +} + static void vmx_set_tsc_offset(struct vcpu *v, u64 offset, u64 at_tsc) { vmx_vmcs_enter(v); @@ -2016,6 +2026,10 @@ static struct hvm_function_table __initdata vmx_function_table = { .altp2m_vcpu_update_vmfunc_ve = vmx_vcpu_update_vmfunc_ve, .altp2m_vcpu_emulate_ve = vmx_vcpu_emulate_ve, .altp2m_vcpu_emulate_vmfunc = vmx_vcpu_emulate_vmfunc, + .tsc_scaling = { + .max_ratio = VMX_TSC_MULTIPLIER_MAX, + .setup = vmx_setup_tsc_scaling, + }, }; /* Handle VT-d posted-interrupt when VCPU is running. */ @@ -2120,6 +2134,9 @@ const struct hvm_function_table * __init start_vmx(void) && cpu_has_vmx_secondary_exec_control ) vmx_function_table.pvh_supported = 1; + if ( cpu_has_vmx_tsc_scaling ) + vmx_function_table.tsc_scaling.ratio_frac_bits = 48; + setup_vmcs_dump(); return &vmx_function_table; diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h index c5c9328..12209d5 100644 --- a/xen/include/asm-x86/hvm/hvm.h +++ b/xen/include/asm-x86/hvm/hvm.h @@ -231,6 +231,9 @@ struct hvm_function_table { uint8_t ratio_frac_bits; /* maximum-allowed TSC scaling ratio */ uint64_t max_ratio; + + /* Architecture function to setup TSC scaling ratio */ + void (*setup)(struct vcpu *v); } tsc_scaling; }; diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index a5e7aee..0d7c6d2 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -237,6 +237,7 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 #define SECONDARY_EXEC_XSAVES 0x00100000 #define SECONDARY_EXEC_PCOMMIT 0x00200000 +#define SECONDARY_EXEC_TSC_SCALING 0x02000000 extern u32 vmx_secondary_exec_control; #define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001 @@ -259,6 +260,8 @@ extern u64 vmx_ept_vpid_cap; #define VMX_MISC_CR3_TARGET 0x01ff0000 #define VMX_MISC_VMWRITE_ALL 0x20000000 +#define VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL + #define cpu_has_wbinvd_exiting \ (vmx_secondary_exec_control & SECONDARY_EXEC_WBINVD_EXITING) #define cpu_has_vmx_virtualize_apic_accesses \ @@ -306,6 +309,9 @@ extern u64 vmx_ept_vpid_cap; (vmx_secondary_exec_control & SECONDARY_EXEC_XSAVES) #define cpu_has_vmx_pcommit \ (vmx_secondary_exec_control & SECONDARY_EXEC_PCOMMIT) +#define cpu_has_vmx_tsc_scaling \ + (vmx_secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) + #define VMCS_RID_TYPE_MASK 0x80000000 /* GUEST_INTERRUPTIBILITY_INFO flags. */ @@ -380,6 +386,7 @@ enum vmcs_field { VMWRITE_BITMAP = 0x00002028, VIRT_EXCEPTION_INFO = 0x0000202a, XSS_EXIT_BITMAP = 0x0000202c, + TSC_MULTIPLIER = 0x00002032, GUEST_PHYSICAL_ADDRESS = 0x00002400, VMCS_LINK_POINTER = 0x00002800, GUEST_IA32_DEBUGCTL = 0x00002802,