From patchwork Wed Mar 2 07:34:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 8478441 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 34F0A9FBE7 for ; Wed, 2 Mar 2016 07:38:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3174C20383 for ; Wed, 2 Mar 2016 07:38:28 +0000 (UTC) Received: from lists.xen.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2DBCB2038E for ; Wed, 2 Mar 2016 07:38:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1ab1KJ-0004nH-55; Wed, 02 Mar 2016 07:36:07 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.84) (envelope-from ) id 1ab1KH-0004mi-Ge for xen-devel@lists.xen.org; Wed, 02 Mar 2016 07:36:05 +0000 Received: from [85.158.137.68] by server-3.bemta-3.messagelabs.com id 65/9D-03294-4E796D65; Wed, 02 Mar 2016 07:36:04 +0000 X-Env-Sender: zhaoshenglong@huawei.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1456904159!26249679!1 X-Originating-IP: [119.145.14.66] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTE5LjE0NS4xNC42NiA9PiA4NTI3\n X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 60763 invoked from network); 2 Mar 2016 07:36:03 -0000 Received: from szxga03-in.huawei.com (HELO szxga03-in.huawei.com) (119.145.14.66) by server-5.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 2 Mar 2016 07:36:03 -0000 Received: from 172.24.1.47 (EHLO SZXEML424-HUB.china.huawei.com) ([172.24.1.47]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BXB04012; Wed, 02 Mar 2016 15:35:42 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML424-HUB.china.huawei.com (10.82.67.153) with Microsoft SMTP Server id 14.3.235.1; Wed, 2 Mar 2016 15:35:19 +0800 From: Shannon Zhao To: Date: Wed, 2 Mar 2016 15:34:36 +0800 Message-ID: <1456904083-13168-11-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1456904083-13168-1-git-send-email-zhaoshenglong@huawei.com> References: <1456904083-13168-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.56D697D2.0055, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 5cdd8bbb408877d8f2ad39d1aec6ec9a Cc: zhaoshenglong@huawei.com, stefano.stabellini@citrix.com, ian.campbell@citrix.com, shannon.zhao@linaro.org Subject: [Xen-devel] [PATCH v8 10/17] arm/gic-v2: Add ACPI boot support for GICv2 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Parth Dixit ACPI on Xen hypervisor uses MADT table for proper GIC initialization. First get the GIC version from GIC Distributor. Then parse GIC related subtables, collect CPU interface and distributor addresses and call driver initialization function (which is hardware abstraction agnostic). In a similar way, FDT initialize GICv2. Signed-off-by: Parth Dixit Signed-off-by: Shannon Zhao Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v2.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 116 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 668b863..0fcb894 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include #include @@ -36,6 +38,7 @@ #include #include +#include /* * LR register definitions are GIC v2 specific. @@ -681,11 +684,108 @@ static void __init gicv2_dt_init(void) csize, vsize); } +#ifdef CONFIG_ACPI +static int __init +gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, + const unsigned long end) +{ + static int cpu_base_assigned = 0; + struct acpi_madt_generic_interrupt *processor = + container_of(header, struct acpi_madt_generic_interrupt, header); + + if ( BAD_MADT_ENTRY(processor, end) ) + return -EINVAL; + + /* Read from APIC table and fill up the GIC variables */ + if ( cpu_base_assigned == 0 ) + { + cbase = processor->base_address; + csize = SZ_8K; + hbase = processor->gich_base_address; + vbase = processor->gicv_base_address; + gicv2_info.maintenance_irq = processor->vgic_interrupt; + + if ( processor->flags & ACPI_MADT_VGIC_IRQ_MODE ) + irq_set_type(gicv2_info.maintenance_irq, IRQ_TYPE_EDGE_BOTH); + else + irq_set_type(gicv2_info.maintenance_irq, IRQ_TYPE_LEVEL_MASK); + + cpu_base_assigned = 1; + } + else + { + if ( cbase != processor->base_address + || hbase != processor->gich_base_address + || vbase != processor->gicv_base_address + || gicv2_info.maintenance_irq != processor->vgic_interrupt ) + { + printk("GICv2: GICC entries are not same in MADT table\n"); + return -EINVAL; + } + } + + return 0; +} + +static int __init +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_distributor *dist = + container_of(header, struct acpi_madt_generic_distributor, header); + + if ( BAD_MADT_ENTRY(dist, end) ) + return -EINVAL; + + dbase = dist->base_address; + + return 0; +} + +static void __init gicv2_acpi_init(void) +{ + acpi_status status; + struct acpi_table_header *table; + int count; + + status = acpi_get_table(ACPI_SIG_MADT, 0, &table); + + if ( ACPI_FAILURE(status) ) + { + const char *msg = acpi_format_exception(status); + + panic("GICv2: Failed to get MADT table, %s", msg); + } + + /* Collect CPU base addresses */ + count = acpi_parse_entries(ACPI_SIG_MADT, sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_cpu, table, + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); + if ( count <= 0 ) + panic("GICv2: No valid GICC entries exists"); + + /* + * Find distributor base address. We expect one distributor entry since + * ACPI 5.0 spec neither support multi-GIC instances nor GIC cascade. + */ + count = acpi_parse_entries(ACPI_SIG_MADT, sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_distributor, table, + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); + if ( count <= 0 ) + panic("GICv2: No valid GICD entries exists"); +} +#else +static void __init gicv2_acpi_init(void) { } +#endif + static int __init gicv2_init(void) { uint32_t aliased_offset = 0; - gicv2_dt_init(); + if ( acpi_disabled ) + gicv2_dt_init(); + else + gicv2_acpi_init(); printk("GICv2 initialization:\n" " gic_dist_addr=%"PRIpaddr"\n" @@ -793,6 +893,21 @@ DT_DEVICE_START(gicv2, "GICv2", DEVICE_GIC) .init = gicv2_dt_preinit, DT_DEVICE_END +#ifdef CONFIG_ACPI +/* Set up the GIC */ +static int __init gicv2_acpi_preinit(const void *data) +{ + gicv2_info.hw_version = GIC_V2; + register_gic_ops(&gicv2_ops); + + return 0; +} + +ACPI_DEVICE_START(agicv2, "GICv2", DEVICE_GIC) + .class_type = ACPI_MADT_GIC_VERSION_V2, + .init = gicv2_acpi_preinit, +ACPI_DEVICE_END +#endif /* * Local variables: * mode: C