From patchwork Wed Mar 23 16:36:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 8651541 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 648AD9FDD5 for ; Wed, 23 Mar 2016 16:39:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 007DE203ED for ; Wed, 23 Mar 2016 16:39:11 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6B8120398 for ; Wed, 23 Mar 2016 16:39:08 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1aillv-0001uV-7X; Wed, 23 Mar 2016 16:36:39 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1aillu-0001qE-1S for xen-devel@lists.xen.org; Wed, 23 Mar 2016 16:36:38 +0000 Received: from [85.158.139.211] by server-5.bemta-5.messagelabs.com id BA/AF-03597-516C2F65; Wed, 23 Mar 2016 16:36:37 +0000 X-Env-Sender: prvs=883e14dc5=Andrew.Cooper3@citrix.com X-Msg-Ref: server-8.tower-206.messagelabs.com!1458750992!30817161!4 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22942 invoked from network); 23 Mar 2016 16:36:36 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-8.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 23 Mar 2016 16:36:36 -0000 X-IronPort-AV: E=Sophos;i="5.24,383,1454976000"; d="scan'208";a="341508155" From: Andrew Cooper To: Xen-devel Date: Wed, 23 Mar 2016 16:36:09 +0000 Message-ID: <1458750989-28967-7-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458750989-28967-1-git-send-email-andrew.cooper3@citrix.com> References: <1458750989-28967-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Andrew Cooper , Jan Beulich Subject: [Xen-devel] [PATCH v4 06/26] xen/x86: Annotate VM applicability in featureset X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use attributes to specify whether a feature is applicable to be exposed to: 1) All guests 2) HVM guests 3) HVM HAP guests and, via absence of an attribute, to no guests. There is no current need for other categories (e.g. PV-only features), and such categories should not be introduced if possible. These categories follow from the fact that, with increased hardware support, a guest gets more features to use. These settings are derived from the existing code in {pv,hvm}_cpuid(), and xc_cpuid_x86.c. One notable exception is EXTAPIC which was previously erroneously exposed to guests. PV guests don't get to use the APIC and the HVM APIC emulation doesn't support extended space. Signed-off-by: Andrew Cooper Reviewed-by: Konrad Rzeszutek Wilk --- CC: Jan Beulich v2: * Annotate features using a magic comment and autogeneration. v3: * Rebase over the new namespaceing changes. * Expand commit message. * Correct PSE36 to being a HAP-only feature. v4: * Re-break PSE36. * Hide LWP from PV guests. --- xen/include/public/arch-x86/cpufeatureset.h | 187 ++++++++++++++-------------- xen/tools/gen-cpuid.py | 30 ++++- 2 files changed, 125 insertions(+), 92 deletions(-) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 8308972..75dd2ac 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -81,135 +81,140 @@ enum { * This bit has special properties and is not a straight indication of a * piece of new functionality. Xen will handle these differently, * and may override toolstack settings completely. + * + * Applicability to guests: 'A', 'S' or 'H' + * 'A' = All guests. + * 'S' = All HVM guests (not PV guests). + * 'H' = HVM HAP guests (not PV or HVM Shadow guests). */ /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */ -XEN_CPUFEATURE(FPU, 0*32+ 0) /* Onboard FPU */ -XEN_CPUFEATURE(VME, 0*32+ 1) /* Virtual Mode Extensions */ -XEN_CPUFEATURE(DE, 0*32+ 2) /* Debugging Extensions */ -XEN_CPUFEATURE(PSE, 0*32+ 3) /* Page Size Extensions */ -XEN_CPUFEATURE(TSC, 0*32+ 4) /* Time Stamp Counter */ -XEN_CPUFEATURE(MSR, 0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */ -XEN_CPUFEATURE(PAE, 0*32+ 6) /* Physical Address Extensions */ -XEN_CPUFEATURE(MCE, 0*32+ 7) /* Machine Check Architecture */ -XEN_CPUFEATURE(CX8, 0*32+ 8) /* CMPXCHG8 instruction */ -XEN_CPUFEATURE(APIC, 0*32+ 9) /*! Onboard APIC */ -XEN_CPUFEATURE(SEP, 0*32+11) /* SYSENTER/SYSEXIT */ -XEN_CPUFEATURE(MTRR, 0*32+12) /* Memory Type Range Registers */ -XEN_CPUFEATURE(PGE, 0*32+13) /* Page Global Enable */ -XEN_CPUFEATURE(MCA, 0*32+14) /* Machine Check Architecture */ -XEN_CPUFEATURE(CMOV, 0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ -XEN_CPUFEATURE(PAT, 0*32+16) /* Page Attribute Table */ -XEN_CPUFEATURE(PSE36, 0*32+17) /* 36-bit PSEs */ -XEN_CPUFEATURE(CLFLUSH, 0*32+19) /* CLFLUSH instruction */ +XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */ +XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */ +XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */ +XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */ +XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */ +XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */ +XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */ +XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ +XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */ +XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */ +XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */ +XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ +XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */ +XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */ +XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ +XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */ +XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */ +XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */ XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ -XEN_CPUFEATURE(ACPI, 0*32+22) /* ACPI via MSR */ -XEN_CPUFEATURE(MMX, 0*32+23) /* Multimedia Extensions */ -XEN_CPUFEATURE(FXSR, 0*32+24) /* FXSAVE and FXRSTOR instructions */ -XEN_CPUFEATURE(SSE, 0*32+25) /* Streaming SIMD Extensions */ -XEN_CPUFEATURE(SSE2, 0*32+26) /* Streaming SIMD Extensions-2 */ -XEN_CPUFEATURE(HTT, 0*32+28) /*! Hyper-Threading Technology */ +XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */ +XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */ +XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */ +XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */ +XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */ +XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */ XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */ XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */ /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */ -XEN_CPUFEATURE(SSE3, 1*32+ 0) /* Streaming SIMD Extensions-3 */ -XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /* Carry-less mulitplication */ +XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */ +XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less mulitplication */ XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */ XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */ XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */ -XEN_CPUFEATURE(VMX, 1*32+ 5) /* Virtual Machine Extensions */ +XEN_CPUFEATURE(VMX, 1*32+ 5) /*S Virtual Machine Extensions */ XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */ XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */ XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */ -XEN_CPUFEATURE(SSSE3, 1*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */ -XEN_CPUFEATURE(FMA, 1*32+12) /* Fused Multiply Add */ -XEN_CPUFEATURE(CX16, 1*32+13) /* CMPXCHG16B */ +XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */ +XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ +XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */ -XEN_CPUFEATURE(PCID, 1*32+17) /* Process Context ID */ +XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */ XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */ -XEN_CPUFEATURE(SSE4_1, 1*32+19) /* Streaming SIMD Extensions 4.1 */ -XEN_CPUFEATURE(SSE4_2, 1*32+20) /* Streaming SIMD Extensions 4.2 */ -XEN_CPUFEATURE(X2APIC, 1*32+21) /*! Extended xAPIC */ -XEN_CPUFEATURE(MOVBE, 1*32+22) /* movbe instruction */ -XEN_CPUFEATURE(POPCNT, 1*32+23) /* POPCNT instruction */ -XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /* TSC Deadline Timer */ -XEN_CPUFEATURE(AESNI, 1*32+25) /* AES instructions */ -XEN_CPUFEATURE(XSAVE, 1*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ +XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */ +XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */ +XEN_CPUFEATURE(X2APIC, 1*32+21) /*!A Extended xAPIC */ +XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */ +XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */ +XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */ +XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */ +XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */ XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */ -XEN_CPUFEATURE(AVX, 1*32+28) /* Advanced Vector Extensions */ -XEN_CPUFEATURE(F16C, 1*32+29) /* Half-precision convert instruction */ -XEN_CPUFEATURE(RDRAND, 1*32+30) /* Digital Random Number Generator */ -XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*! Running under some hypervisor */ +XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */ +XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */ +XEN_CPUFEATURE(RDRAND, 1*32+30) /*A Digital Random Number Generator */ +XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*!A Running under some hypervisor */ /* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */ -XEN_CPUFEATURE(SYSCALL, 2*32+11) /* SYSCALL/SYSRET */ -XEN_CPUFEATURE(NX, 2*32+20) /* Execute Disable */ -XEN_CPUFEATURE(MMXEXT, 2*32+22) /* AMD MMX extensions */ -XEN_CPUFEATURE(FFXSR, 2*32+25) /* FFXSR instruction optimizations */ -XEN_CPUFEATURE(PAGE1GB, 2*32+26) /* 1Gb large page support */ -XEN_CPUFEATURE(RDTSCP, 2*32+27) /* RDTSCP */ -XEN_CPUFEATURE(LM, 2*32+29) /* Long Mode (x86-64) */ -XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /* AMD 3DNow! extensions */ -XEN_CPUFEATURE(3DNOW, 2*32+31) /* 3DNow! */ +XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */ +XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */ +XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */ +XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */ +XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */ +XEN_CPUFEATURE(RDTSCP, 2*32+27) /*S RDTSCP */ +XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ +XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */ +XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */ /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */ -XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /* LAHF/SAHF in long mode */ -XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*! If yes HyperThreading not valid */ -XEN_CPUFEATURE(SVM, 3*32+ 2) /* Secure virtual machine */ +XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */ +XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */ +XEN_CPUFEATURE(SVM, 3*32+ 2) /*S Secure virtual machine */ XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ -XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /* CR8 in 32-bit mode */ -XEN_CPUFEATURE(ABM, 3*32+ 5) /* Advanced bit manipulation */ -XEN_CPUFEATURE(SSE4A, 3*32+ 6) /* SSE-4A */ -XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /* Misaligned SSE mode */ -XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /* 3DNow prefetch instructions */ +XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */ +XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */ +XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */ +XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */ +XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */ XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */ -XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */ -XEN_CPUFEATURE(XOP, 3*32+11) /* extended AVX instructions */ +XEN_CPUFEATURE(IBS, 3*32+10) /*S Instruction Based Sampling */ +XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ -XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ -XEN_CPUFEATURE(FMA4, 3*32+16) /* 4 operands MAC instructions */ +XEN_CPUFEATURE(LWP, 3*32+15) /*S Light Weight Profiling */ +XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ -XEN_CPUFEATURE(TBM, 3*32+21) /* trailing bit manipulations */ +XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ -XEN_CPUFEATURE(DBEXT, 3*32+26) /* data breakpoint extension */ +XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */ /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ -XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /* XSAVEOPT instruction */ -XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /* XSAVEC/XRSTORC instructions */ -XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /* XGETBV with %ecx=1 */ -XEN_CPUFEATURE(XSAVES, 4*32+ 3) /* XSAVES/XRSTORS instructions */ +XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */ +XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ +XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ +XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ -XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ -XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /* TSC_ADJUST MSR available */ -XEN_CPUFEATURE(BMI1, 5*32+ 3) /* 1st bit manipulation extensions */ -XEN_CPUFEATURE(HLE, 5*32+ 4) /* Hardware Lock Elision */ -XEN_CPUFEATURE(AVX2, 5*32+ 5) /* AVX2 instructions */ +XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ +XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */ +XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */ +XEN_CPUFEATURE(HLE, 5*32+ 4) /*A Hardware Lock Elision */ +XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */ XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */ -XEN_CPUFEATURE(SMEP, 5*32+ 7) /* Supervisor Mode Execution Protection */ -XEN_CPUFEATURE(BMI2, 5*32+ 8) /* 2nd bit manipulation extensions */ -XEN_CPUFEATURE(ERMS, 5*32+ 9) /* Enhanced REP MOVSB/STOSB */ -XEN_CPUFEATURE(INVPCID, 5*32+10) /* Invalidate Process Context ID */ -XEN_CPUFEATURE(RTM, 5*32+11) /* Restricted Transactional Memory */ +XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */ +XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */ +XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */ +XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */ +XEN_CPUFEATURE(RTM, 5*32+11) /*A Restricted Transactional Memory */ XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ -XEN_CPUFEATURE(MPX, 5*32+14) /* Memory Protection Extensions */ +XEN_CPUFEATURE(MPX, 5*32+14) /*S Memory Protection Extensions */ XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ -XEN_CPUFEATURE(RDSEED, 5*32+18) /* RDSEED instruction */ -XEN_CPUFEATURE(ADX, 5*32+19) /* ADCX, ADOX instructions */ -XEN_CPUFEATURE(SMAP, 5*32+20) /* Supervisor Mode Access Prevention */ -XEN_CPUFEATURE(PCOMMIT, 5*32+22) /* PCOMMIT instruction */ -XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /* CLFLUSHOPT instruction */ -XEN_CPUFEATURE(CLWB, 5*32+24) /* CLWB instruction */ -XEN_CPUFEATURE(SHA, 5*32+29) /* SHA1 & SHA256 instructions */ +XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ +XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ +XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ +XEN_CPUFEATURE(PCOMMIT, 5*32+22) /*A PCOMMIT instruction */ +XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ +XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ +XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ -XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /* PREFETCHWT1 instruction */ -XEN_CPUFEATURE(PKU, 6*32+ 3) /* Protection Keys for Userspace */ +XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ +XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ @@ -217,7 +222,7 @@ XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ -XEN_CPUFEATURE(CLZERO, 8*32+ 0) /* CLZERO instruction */ +XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ #endif /* XEN_CPUFEATURE */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 5076fb9..4fd603d 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -17,12 +17,18 @@ class State(object): # State parsed from input self.names = {} # Name => value mapping self.raw_special = set() + self.raw_pv = set() + self.raw_hvm_shadow = set() + self.raw_hvm_hap = set() # State calculated self.nr_entries = 0 # Number of words in a featureset self.common_1d = 0 # Common features between 1d and e1d self.known = [] # All known features self.special = [] # Features with special semantics + self.pv = [] + self.hvm_shadow = [] + self.hvm_hap = [] def parse_definitions(state): """ @@ -32,7 +38,7 @@ def parse_definitions(state): feat_regex = re.compile( r"^XEN_CPUFEATURE\(([A-Z0-9_]+)," "\s+([\s\d]+\*[\s\d]+\+[\s\d]+)\)" - "\s+/\*([!]*) .*$") + "\s+/\*([\w!]*) .*$") this = sys.modules[__name__] @@ -72,6 +78,16 @@ def parse_definitions(state): if a == "!": state.raw_special.add(val) + elif a in "ASH": + if a == "A": + state.raw_pv.add(val) + state.raw_hvm_shadow.add(val) + state.raw_hvm_hap.add(val) + elif attr == "S": + state.raw_hvm_shadow.add(val) + state.raw_hvm_hap.add(val) + elif attr == "H": + state.raw_hvm_hap.add(val) else: raise Fail("Unrecognised attribute '%s' for %s" % (a, name)) @@ -124,6 +140,9 @@ def crunch_numbers(state): state.common_1d = featureset_to_uint32s(common_1d, 1)[0] state.special = featureset_to_uint32s(state.raw_special, nr_entries) + state.pv = featureset_to_uint32s(state.raw_pv, nr_entries) + state.hvm_shadow = featureset_to_uint32s(state.raw_hvm_shadow, nr_entries) + state.hvm_hap = featureset_to_uint32s(state.raw_hvm_hap, nr_entries) def write_results(state): @@ -145,10 +164,19 @@ def write_results(state): #define INIT_KNOWN_FEATURES { \\\n%s\n} #define INIT_SPECIAL_FEATURES { \\\n%s\n} + +#define INIT_PV_FEATURES { \\\n%s\n} + +#define INIT_HVM_SHADOW_FEATURES { \\\n%s\n} + +#define INIT_HVM_HAP_FEATURES { \\\n%s\n} """ % (state.nr_entries, state.common_1d, format_uint32s(state.known, 4), format_uint32s(state.special, 4), + format_uint32s(state.pv, 4), + format_uint32s(state.hvm_shadow, 4), + format_uint32s(state.hvm_hap, 4), )) state.output.write(