From patchwork Thu Mar 31 08:57:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shuai Ruan X-Patchwork-Id: 8708811 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1B182C0553 for ; Thu, 31 Mar 2016 08:57:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 29BBE20221 for ; Thu, 31 Mar 2016 08:57:26 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30389201FE for ; Thu, 31 Mar 2016 08:57:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1alYNY-0000YJ-KA; Thu, 31 Mar 2016 08:55:00 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1alYNX-0000XP-GQ for xen-devel@lists.xen.org; Thu, 31 Mar 2016 08:54:59 +0000 Received: from [85.158.143.35] by server-3.bemta-6.messagelabs.com id 28/60-07120-2E5ECF65; Thu, 31 Mar 2016 08:54:58 +0000 X-Env-Sender: shuai.ruan@linux.intel.com X-Msg-Ref: server-10.tower-21.messagelabs.com!1459414494!6674103!4 X-Originating-IP: [134.134.136.65] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.11; banners=-,-,- X-VirusChecked: Checked Received: (qmail 18264 invoked from network); 31 Mar 2016 08:54:58 -0000 Received: from mga03.intel.com (HELO mga03.intel.com) (134.134.136.65) by server-10.tower-21.messagelabs.com with SMTP; 31 Mar 2016 08:54:58 -0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP; 31 Mar 2016 01:54:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,421,1455004800"; d="scan'208";a="76441794" Received: from rs-vmm.bj.intel.com ([10.238.135.55]) by fmsmga004.fm.intel.com with ESMTP; 31 Mar 2016 01:54:56 -0700 From: Shuai Ruan To: xen-devel@lists.xen.org Date: Thu, 31 Mar 2016 16:57:37 +0800 Message-Id: <1459414657-7558-4-git-send-email-shuai.ruan@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459414657-7558-1-git-send-email-shuai.ruan@linux.intel.com> References: <1459414657-7558-1-git-send-email-shuai.ruan@linux.intel.com> Cc: andrew.cooper3@citrix.com, keir@xen.org, jbeulich@suse.com Subject: [Xen-devel] [PATCH V7 3/3] x86/xsaves: ebx may return wrong value using CPUID eax=0xdh, ecx =1 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shuai Ruan Refer to SDM 13.4.3 Extended Region of an XSAVE Area. The value return by ecx[1] with cpuid function 0xdh and sub-fucntion i (i>1) indicates the alignment of the state component i when the compacted format of the extended region of an xsave area is used. So when hvm/pv guest using CPUID eax=0xdh,ecx=1 to get the size of area used for compacted format, we need to take alignment into consideration. tools side is fixed by "tools/libxc: Calculate xstate cpuid leaf from guest information" by Andrew Cooper Signed-off-by: Shuai Ruan --- v2: Address comments by Jan: 1. take alignment into consideration in pv_cpuid. 2. fix coding style issues xen/arch/x86/hvm/hvm.c | 6 +++++- xen/arch/x86/traps.c | 12 ++++++++++++ xen/arch/x86/xstate.c | 2 +- xen/include/asm-x86/xstate.h | 1 + 4 files changed, 19 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5aef3cb..c6cd4fb 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4743,14 +4743,18 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, } if ( count == 1 ) { - if ( cpu_has_xsaves && cpu_has_vmx_xsaves ) + if ( (cpu_has_xsaves && cpu_has_vmx_xsaves) || cpu_has_xsavec ) { *ebx = XSTATE_AREA_MIN_SIZE; if ( v->arch.xcr0 | v->arch.hvm_vcpu.msr_xss ) for ( sub_leaf = 2; sub_leaf < 63; sub_leaf++ ) if ( (v->arch.xcr0 | v->arch.hvm_vcpu.msr_xss) & (1ULL << sub_leaf) ) + { + if ( test_bit(sub_leaf, &xstate_align) ) + *ebx = ROUNDUP(*ebx, 64); *ebx += xstate_sizes[sub_leaf]; + } } else *ebx = *ecx = *edx = 0; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 6fbb1cf..8694da6 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1020,6 +1020,18 @@ void pv_cpuid(struct cpu_user_regs *regs) a &= (boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_XSAVEOPT)] & ~cpufeat_mask(X86_FEATURE_XSAVES)); b = c = d = 0; + if ( cpu_has_xsavec ) + { + b = XSTATE_AREA_MIN_SIZE; + if ( curr->arch.xcr0 ) + for( subleaf = 2; subleaf < 63; subleaf++ ) + if ( (1ULL << subleaf) & curr->arch.xcr0 ) + { + if ( test_bit(subleaf, &xstate_align) ) + b = ROUNDUP(b, 64); + b += xstate_sizes[subleaf]; + } + } break; } break; diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index f4ea54d..850b778 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -26,7 +26,7 @@ u64 __read_mostly xfeature_mask; static unsigned int *__read_mostly xstate_offsets; unsigned int *__read_mostly xstate_sizes; -static u64 __read_mostly xstate_align; +u64 __read_mostly xstate_align; static unsigned int __read_mostly xstate_features; static uint32_t __read_mostly mxcsr_mask = 0x0000ffbf; diff --git a/xen/include/asm-x86/xstate.h b/xen/include/asm-x86/xstate.h index 91d1c39..535443a 100644 --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -50,6 +50,7 @@ #define XSTATE_ALIGN64 (1U << 1) extern u64 xfeature_mask; +extern u64 xstate_align; extern unsigned int *xstate_sizes; /* extended state save area */