From patchwork Fri Apr 8 20:31:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 8786251 Return-Path: X-Original-To: patchwork-xen-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 40B299F36E for ; Fri, 8 Apr 2016 21:01:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2785B202EB for ; Fri, 8 Apr 2016 21:01:13 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 12EB120222 for ; Fri, 8 Apr 2016 21:01:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1aodUN-0002LH-HC; Fri, 08 Apr 2016 20:58:47 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1aodUL-0002KQ-Uf for xen-devel@lists.xen.org; Fri, 08 Apr 2016 20:58:46 +0000 Received: from [85.158.143.35] by server-2.bemta-6.messagelabs.com id 25/3E-09532-58B18075; Fri, 08 Apr 2016 20:58:45 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjkeJIrShJLcpLzFFi42JxWrrBXrdFmiP c4FWjvsWSj4tZHBg9ju7+zRTAGMWamZeUX5HAmvFt7gXmgrdmFe8PfmZrYFyk2sXIySEh4C/x dNNVdhCbTUBfYveLT0wgtoiAusTpjousXYwcHMwCuhKrfmqAhIUFIiVmdvxlAbFZBFQkXsx7z gZi8wp4SRz/tJsdYqScxPnjP5lBbE6g+JltZ1hBbCEBT4nLM+ezQNhqEtf6L7FD9ApKnJz5BC zOLCAhcfDFC2aQtRIC3BJ/u+0nMPLNQlI1C0nVAkamVYzqxalFZalFusZ6SUWZ6RkluYmZObq GBmZ6uanFxYnpqTmJScV6yfm5mxiB4cQABDsYO/45HWKU5GBSEuXd9pA9XIgvKT+lMiOxOCO+ qDQntfgQowwHh5IE71QpjnAhwaLU9NSKtMwcYGDDpCU4eJREeMtB0rzFBYm5xZnpEKlTjIpS4 rzVIAkBkERGaR5cGyyaLjHKSgnzMgIdIsRTkFqUm1mCKv+KUZyDUUmYtxBkCk9mXgnc9FdAi5 mAFl/gZwNZXJKIkJJqYNzMuHjJ/O0rxXUYOlcbNa7t1dTll9y2wzz1qSi7+tNXtUcW9s3UuDV /0aYN/GpXz1g941iiNmXaxBr1ZI6bTyPexT+cwp2wIcWnxWPVinaf1V9Mf7ZvvTPfVpm12/mv bn76rp5zp3fxCV+37l+17MWv8AkOzqoF1ZMFGlZ9+7PowQ+7u61bJ6sosRRnJBpqMRcVJwIAU 7p2UqECAAA= X-Env-Sender: prvs=8997c7931=Andrew.Cooper3@citrix.com X-Msg-Ref: server-16.tower-21.messagelabs.com!1460149123!3924205!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 8.28; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11615 invoked from network); 8 Apr 2016 20:58:44 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-16.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 8 Apr 2016 20:58:44 -0000 X-IronPort-AV: E=Sophos;i="5.24,454,1454976000"; d="scan'208";a="352601097" From: Andrew Cooper To: Xen-devel Date: Fri, 8 Apr 2016 21:31:49 +0100 Message-ID: <1460147517-11706-14-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1460147517-11706-1-git-send-email-andrew.cooper3@citrix.com> References: <1460147517-11706-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Andrew Cooper Subject: [Xen-devel] [PATCH v6 13/21] x86/domctl: Update PV domain cpumasks when setting cpuid policy X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows PV domains with different featuresets to observe different values from a native cpuid instruction, on supporting hardware. It is important to leak the host view of X2APIC, HTT and CMP_LEGACY through to guests, even though they could be hidden. These flags affect how to interpret other cpuid leaves which are not maskable. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Reviewed-by: Konrad Rzeszutek Wilk --- v2: * Use switch() rather than if/elseif chain * Clamp to static PV featuremask v3: * Only set a shadow cpumask if it is available in hardware. This causes fewer branches in the context switch. * Fix interaction between fastforward bits and override MSR. * Fix up the cross-vendor case. * Fix the host view of HTT/CMP_LEGACY. v4: * More comments explaining the masking MSRs behaviour. * s/CPU/CPUID/ * Leak host X2APIC. v5: * Fix commit message wrt X2APIC. --- xen/arch/x86/domctl.c | 138 +++++++++++++++++++++++++++++++++++++++ xen/include/asm-x86/cpufeature.h | 1 + 2 files changed, 139 insertions(+) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index e5180ef..cba1e37 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -36,6 +36,7 @@ #include #include #include +#include static int gdbsx_guest_mem_io(domid_t domid, struct xen_domctl_gdbsx_memio *iop) { @@ -87,6 +88,143 @@ static void update_domain_cpuid_info(struct domain *d, d->arch.x86_model = (ctl->eax >> 4) & 0xf; if ( d->arch.x86 >= 0x6 ) d->arch.x86_model |= (ctl->eax >> 12) & 0xf0; + + if ( is_pv_domain(d) && ((levelling_caps & LCAP_1cd) == LCAP_1cd) ) + { + uint64_t mask = cpuidmask_defaults._1cd; + uint32_t ecx = ctl->ecx & pv_featureset[FEATURESET_1c]; + uint32_t edx = ctl->edx & pv_featureset[FEATURESET_1d]; + + /* + * Must expose hosts HTT and X2APIC value so a guest using native + * CPUID can correctly interpret other leaves which cannot be + * masked. + */ + if ( cpu_has_x2apic ) + ecx |= cpufeat_mask(X86_FEATURE_X2APIC); + if ( cpu_has_htt ) + edx |= cpufeat_mask(X86_FEATURE_HTT); + + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + /* + * Intel masking MSRs are documented as AND masks. + * Experimentally, they are applied before OSXSAVE and APIC + * are fast-forwarded from real hardware state. + */ + mask &= ((uint64_t)edx << 32) | ecx; + break; + + case X86_VENDOR_AMD: + mask &= ((uint64_t)ecx << 32) | edx; + + /* + * AMD masking MSRs are documented as overrides. + * Experimentally, fast-forwarding of the OSXSAVE and APIC + * bits from real hardware state only occurs if the MSR has + * the respective bits set. + */ + if ( ecx & cpufeat_mask(X86_FEATURE_XSAVE) ) + ecx = cpufeat_mask(X86_FEATURE_OSXSAVE); + else + ecx = 0; + edx = cpufeat_mask(X86_FEATURE_APIC); + + mask |= ((uint64_t)ecx << 32) | edx; + break; + } + + d->arch.pv_domain.cpuidmasks->_1cd = mask; + } + break; + + case 6: + if ( is_pv_domain(d) && ((levelling_caps & LCAP_6c) == LCAP_6c) ) + { + uint64_t mask = cpuidmask_defaults._6c; + + if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) + mask &= (~0ULL << 32) | ctl->ecx; + + d->arch.pv_domain.cpuidmasks->_6c = mask; + } + break; + + case 7: + if ( ctl->input[1] != 0 ) + break; + + if ( is_pv_domain(d) && ((levelling_caps & LCAP_7ab0) == LCAP_7ab0) ) + { + uint64_t mask = cpuidmask_defaults._7ab0; + uint32_t eax = ctl->eax; + uint32_t ebx = ctl->ebx & pv_featureset[FEATURESET_7b0]; + + if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) + mask &= ((uint64_t)eax << 32) | ebx; + + d->arch.pv_domain.cpuidmasks->_7ab0 = mask; + } + break; + + case 0xd: + if ( ctl->input[1] != 1 ) + break; + + if ( is_pv_domain(d) && ((levelling_caps & LCAP_Da1) == LCAP_Da1) ) + { + uint64_t mask = cpuidmask_defaults.Da1; + uint32_t eax = ctl->eax & pv_featureset[FEATURESET_Da1]; + + if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) + mask &= (~0ULL << 32) | eax; + + d->arch.pv_domain.cpuidmasks->Da1 = mask; + } + break; + + case 0x80000001: + if ( is_pv_domain(d) && ((levelling_caps & LCAP_e1cd) == LCAP_e1cd) ) + { + uint64_t mask = cpuidmask_defaults.e1cd; + uint32_t ecx = ctl->ecx & pv_featureset[FEATURESET_e1c]; + uint32_t edx = ctl->edx & pv_featureset[FEATURESET_e1d]; + + /* + * Must expose hosts CMP_LEGACY value so a guest using native + * CPUID can correctly interpret other leaves which cannot be + * masked. + */ + if ( cpu_has_cmp_legacy ) + ecx |= cpufeat_mask(X86_FEATURE_CMP_LEGACY); + + /* If not emulating AMD, clear the duplicated features in e1d. */ + if ( d->arch.x86_vendor != X86_VENDOR_AMD ) + edx &= ~CPUID_COMMON_1D_FEATURES; + + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + mask &= ((uint64_t)edx << 32) | ecx; + break; + + case X86_VENDOR_AMD: + mask &= ((uint64_t)ecx << 32) | edx; + + /* + * Fast-forward bits - Must be set in the masking MSR for + * fast-forwarding to occur in hardware. + */ + ecx = 0; + edx = cpufeat_mask(X86_FEATURE_APIC); + + mask |= ((uint64_t)ecx << 32) | edx; + break; + } + + d->arch.pv_domain.cpuidmasks->e1cd = mask; + } break; } } diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 9a93799..97c7e9e 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -84,6 +84,7 @@ #define cpu_has_monitor boot_cpu_has(X86_FEATURE_MONITOR) #define cpu_has_eist boot_cpu_has(X86_FEATURE_EIST) #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) +#define cpu_has_cmp_legacy boot_cpu_has(X86_FEATURE_CMP_LEGACY) enum _cache_type { CACHE_TYPE_NULL = 0,