| Message ID | 1463395771-16001-1-git-send-email-andrew.cooper3@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, May 16, 2016 at 11:49:31AM +0100, Andrew Cooper wrote: > * Abstract (X86_CR4_SMEP | X86_CR4_SMAP) behind XEN_CR4_PV32_BITS to avoid > opencoding the invidial bits which are fixed up behind a 32bit PV guests > back. > * In the debug case, perform the the AND and CMP on 64bit values rather than > 32bit values, to match the logic in then non-debug case. > * Show cr4_pv32_mask in the BUG register dump > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Wei Liu <wei.liu2@citrix.com> Release-acked-by: Wei Liu <wei.liu2@citrix.com> > --- > CC: Jan Beulich <JBeulich@suse.com> > CC: Wei Liu <wei.liu2@citrix.com> > --- > xen/arch/x86/setup.c | 2 +- > xen/arch/x86/x86_64/compat/entry.S | 8 +++++--- > xen/include/asm-x86/processor.h | 2 ++ > 3 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c > index 4c2d01a..de682e7 100644 > --- a/xen/arch/x86/setup.c > +++ b/xen/arch/x86/setup.c > @@ -1400,7 +1400,7 @@ void __init noreturn __start_xen(unsigned long mbi_p) > if ( cpu_has_smap ) > set_in_cr4(X86_CR4_SMAP); > > - cr4_pv32_mask = mmu_cr4_features & (X86_CR4_SMEP | X86_CR4_SMAP); > + cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS; > > if ( cpu_has_fsgsbase ) > set_in_cr4(X86_CR4_FSGSBASE); > diff --git a/xen/arch/x86/x86_64/compat/entry.S b/xen/arch/x86/x86_64/compat/entry.S > index dbc3984..ee72ece 100644 > --- a/xen/arch/x86/x86_64/compat/entry.S > +++ b/xen/arch/x86/x86_64/compat/entry.S > @@ -204,7 +204,7 @@ ENTRY(cr4_pv32_restore) > push %rdx > GET_CPUINFO_FIELD(cr4, dx) > mov (%rdx), %rax > - test $X86_CR4_SMEP|X86_CR4_SMAP,%eax > + test $XEN_CR4_PV32_BITS, %eax > jnz 0f > or cr4_pv32_mask(%rip), %rax > mov %rax, %cr4 > @@ -215,9 +215,11 @@ ENTRY(cr4_pv32_restore) > #ifndef NDEBUG > /* Check that _all_ of the bits intended to be set actually are. */ > mov %cr4, %rax > - and cr4_pv32_mask(%rip), %eax > - cmp cr4_pv32_mask(%rip), %eax > + and cr4_pv32_mask(%rip), %rax > + cmp cr4_pv32_mask(%rip), %rax > je 1f > + /* Cause cr4_pv32_mask to be visible in the BUG register dump. */ > + mov cr4_pv32_mask(%rip), %rdx > BUG > 1: > #endif > diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h > index 4a6af0f..ddaaf2de 100644 > --- a/xen/include/asm-x86/processor.h > +++ b/xen/include/asm-x86/processor.h > @@ -151,6 +151,8 @@ > > #define XEN_MINIMAL_CR4 (X86_CR4_PGE | X86_CR4_PAE) > > +#define XEN_CR4_PV32_BITS (X86_CR4_SMEP|X86_CR4_SMAP) > + > #define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF| \ > X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \ > X86_EFLAGS_TF) > -- > 2.1.4 >
>>> On 16.05.16 at 12:49, <andrew.cooper3@citrix.com> wrote: > * Abstract (X86_CR4_SMEP | X86_CR4_SMAP) behind XEN_CR4_PV32_BITS to avoid > opencoding the invidial bits which are fixed up behind a 32bit PV guests > back. > * In the debug case, perform the the AND and CMP on 64bit values rather than > 32bit values, to match the logic in then non-debug case. I had intentionally done it that way, as the upper 32 bit can only ever be zero. But anyway, I see it has gone in already. Oddly enough we now even got a push without any fix. Jan > * Show cr4_pv32_mask in the BUG register dump > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> > --- > CC: Jan Beulich <JBeulich@suse.com> > CC: Wei Liu <wei.liu2@citrix.com> > --- > xen/arch/x86/setup.c | 2 +- > xen/arch/x86/x86_64/compat/entry.S | 8 +++++--- > xen/include/asm-x86/processor.h | 2 ++ > 3 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c > index 4c2d01a..de682e7 100644 > --- a/xen/arch/x86/setup.c > +++ b/xen/arch/x86/setup.c > @@ -1400,7 +1400,7 @@ void __init noreturn __start_xen(unsigned long mbi_p) > if ( cpu_has_smap ) > set_in_cr4(X86_CR4_SMAP); > > - cr4_pv32_mask = mmu_cr4_features & (X86_CR4_SMEP | X86_CR4_SMAP); > + cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS; > > if ( cpu_has_fsgsbase ) > set_in_cr4(X86_CR4_FSGSBASE); > diff --git a/xen/arch/x86/x86_64/compat/entry.S > b/xen/arch/x86/x86_64/compat/entry.S > index dbc3984..ee72ece 100644 > --- a/xen/arch/x86/x86_64/compat/entry.S > +++ b/xen/arch/x86/x86_64/compat/entry.S > @@ -204,7 +204,7 @@ ENTRY(cr4_pv32_restore) > push %rdx > GET_CPUINFO_FIELD(cr4, dx) > mov (%rdx), %rax > - test $X86_CR4_SMEP|X86_CR4_SMAP,%eax > + test $XEN_CR4_PV32_BITS, %eax > jnz 0f > or cr4_pv32_mask(%rip), %rax > mov %rax, %cr4 > @@ -215,9 +215,11 @@ ENTRY(cr4_pv32_restore) > #ifndef NDEBUG > /* Check that _all_ of the bits intended to be set actually are. */ > mov %cr4, %rax > - and cr4_pv32_mask(%rip), %eax > - cmp cr4_pv32_mask(%rip), %eax > + and cr4_pv32_mask(%rip), %rax > + cmp cr4_pv32_mask(%rip), %rax > je 1f > + /* Cause cr4_pv32_mask to be visible in the BUG register dump. */ > + mov cr4_pv32_mask(%rip), %rdx > BUG > 1: > #endif > diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h > index 4a6af0f..ddaaf2de 100644 > --- a/xen/include/asm-x86/processor.h > +++ b/xen/include/asm-x86/processor.h > @@ -151,6 +151,8 @@ > > #define XEN_MINIMAL_CR4 (X86_CR4_PGE | X86_CR4_PAE) > > +#define XEN_CR4_PV32_BITS (X86_CR4_SMEP|X86_CR4_SMAP) > + > #define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF| \ > X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \ > X86_EFLAGS_TF) > -- > 2.1.4
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 4c2d01a..de682e7 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1400,7 +1400,7 @@ void __init noreturn __start_xen(unsigned long mbi_p) if ( cpu_has_smap ) set_in_cr4(X86_CR4_SMAP); - cr4_pv32_mask = mmu_cr4_features & (X86_CR4_SMEP | X86_CR4_SMAP); + cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS; if ( cpu_has_fsgsbase ) set_in_cr4(X86_CR4_FSGSBASE); diff --git a/xen/arch/x86/x86_64/compat/entry.S b/xen/arch/x86/x86_64/compat/entry.S index dbc3984..ee72ece 100644 --- a/xen/arch/x86/x86_64/compat/entry.S +++ b/xen/arch/x86/x86_64/compat/entry.S @@ -204,7 +204,7 @@ ENTRY(cr4_pv32_restore) push %rdx GET_CPUINFO_FIELD(cr4, dx) mov (%rdx), %rax - test $X86_CR4_SMEP|X86_CR4_SMAP,%eax + test $XEN_CR4_PV32_BITS, %eax jnz 0f or cr4_pv32_mask(%rip), %rax mov %rax, %cr4 @@ -215,9 +215,11 @@ ENTRY(cr4_pv32_restore) #ifndef NDEBUG /* Check that _all_ of the bits intended to be set actually are. */ mov %cr4, %rax - and cr4_pv32_mask(%rip), %eax - cmp cr4_pv32_mask(%rip), %eax + and cr4_pv32_mask(%rip), %rax + cmp cr4_pv32_mask(%rip), %rax je 1f + /* Cause cr4_pv32_mask to be visible in the BUG register dump. */ + mov cr4_pv32_mask(%rip), %rdx BUG 1: #endif diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h index 4a6af0f..ddaaf2de 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -151,6 +151,8 @@ #define XEN_MINIMAL_CR4 (X86_CR4_PGE | X86_CR4_PAE) +#define XEN_CR4_PV32_BITS (X86_CR4_SMEP|X86_CR4_SMAP) + #define XEN_SYSCALL_MASK (X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF| \ X86_EFLAGS_NT|X86_EFLAGS_DF|X86_EFLAGS_IF| \ X86_EFLAGS_TF)
* Abstract (X86_CR4_SMEP | X86_CR4_SMAP) behind XEN_CR4_PV32_BITS to avoid opencoding the invidial bits which are fixed up behind a 32bit PV guests back. * In the debug case, perform the the AND and CMP on 64bit values rather than 32bit values, to match the logic in then non-debug case. * Show cr4_pv32_mask in the BUG register dump Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> CC: Wei Liu <wei.liu2@citrix.com> --- xen/arch/x86/setup.c | 2 +- xen/arch/x86/x86_64/compat/entry.S | 8 +++++--- xen/include/asm-x86/processor.h | 2 ++ 3 files changed, 8 insertions(+), 4 deletions(-)