diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 344d3ad..7d2641c 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -42,6 +42,7 @@ obj-y += processor.o
 obj-y += smc.o
 obj-$(CONFIG_XSPLICE) += xsplice.o
 obj-y += monitor.o
+obj-y += vm_event.o
 
 #obj-bin-y += ....o
 
diff --git a/xen/arch/arm/vm_event.c b/xen/arch/arm/vm_event.c
new file mode 100644
index 0000000..dcf9f1c
--- /dev/null
+++ b/xen/arch/arm/vm_event.c
@@ -0,0 +1,139 @@
+/*
+ * arch/arm/vm_event.c
+ *
+ * Architecture-specific vm_event handling routines
+ *
+ * Copyright (c) 2016 Tamas K Lengyel (tamas@tklengyel.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public
+ * License v2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <xen/sched.h>
+#include <asm/vm_event.h>
+
+void vm_event_fill_regs(vm_event_request_t *req)
+{
+    const struct cpu_user_regs *regs = guest_cpu_user_regs();
+
+    req->data.regs.arm.cpsr = regs->cpsr;
+    req->data.regs.arm.ttbr0 = READ_SYSREG64(TTBR0_EL1);
+    req->data.regs.arm.ttbr1 = READ_SYSREG64(TTBR1_EL1);
+
+    if ( psr_mode_is_32bit(regs->cpsr) )
+    {
+        req->data.regs.arm.arch.arm32.r0_usr = regs->r0;
+        req->data.regs.arm.arch.arm32.r1_usr = regs->r1;
+        req->data.regs.arm.arch.arm32.r2_usr = regs->r2;
+        req->data.regs.arm.arch.arm32.r3_usr = regs->r3;
+        req->data.regs.arm.arch.arm32.r4_usr = regs->r4;
+        req->data.regs.arm.arch.arm32.r5_usr = regs->r5;
+        req->data.regs.arm.arch.arm32.r6_usr = regs->r6;
+        req->data.regs.arm.arch.arm32.r7_usr = regs->r7;
+        req->data.regs.arm.arch.arm32.r8_usr = regs->r8;
+        req->data.regs.arm.arch.arm32.r9_usr = regs->r9;
+        req->data.regs.arm.arch.arm32.r10_usr = regs->r10;
+        req->data.regs.arm.arch.arm32.r12_usr = regs->r12;
+        req->data.regs.arm.arch.arm32.lr_usr = regs->lr_usr;
+        req->data.regs.arm.arch.arm32.pc = regs->pc32;
+        req->data.regs.arm.arch.arm32.fp = regs->fp;
+        req->data.regs.arm.arch.arm32.sp_usr = regs->sp_usr;
+        req->data.regs.arm.arch.arm32.sp_svc = regs->sp_svc;
+        req->data.regs.arm.arch.arm32.spsr_svc = regs->spsr_svc;
+    }
+#ifdef CONFIG_ARM_64
+    else
+    {
+        req->data.regs.arm.arch.arm64.x0 = regs->x0;
+        req->data.regs.arm.arch.arm64.x1 = regs->x1;
+        req->data.regs.arm.arch.arm64.x2 = regs->x2;
+        req->data.regs.arm.arch.arm64.x3 = regs->x3;
+        req->data.regs.arm.arch.arm64.x4 = regs->x4;
+        req->data.regs.arm.arch.arm64.x5 = regs->x5;
+        req->data.regs.arm.arch.arm64.x6 = regs->x6;
+        req->data.regs.arm.arch.arm64.x7 = regs->x7;
+        req->data.regs.arm.arch.arm64.x8 = regs->x8;
+        req->data.regs.arm.arch.arm64.x9 = regs->x9;
+        req->data.regs.arm.arch.arm64.x10 = regs->x10;
+        req->data.regs.arm.arch.arm64.x16 = regs->x16;
+        req->data.regs.arm.arch.arm64.pc = regs->pc;
+        req->data.regs.arm.arch.arm64.sp_el0 = regs->sp_el0;
+        req->data.regs.arm.arch.arm64.sp_el1 = regs->sp_el1;
+        req->data.regs.arm.arch.arm64.fp = regs->fp;
+        req->data.regs.arm.arch.arm64.lr = regs->lr;
+        req->data.regs.arm.arch.arm64.spsr_el1 = regs->spsr_svc;
+    }
+#endif
+}
+
+void vm_event_set_registers(struct vcpu *v, vm_event_response_t *rsp)
+{
+    struct cpu_user_regs *regs = &v->arch.cpu_info->guest_cpu_user_regs;
+
+    regs->cpsr = rsp->data.regs.arm.cpsr;
+    v->arch.ttbr0 = rsp->data.regs.arm.ttbr0;
+    v->arch.ttbr1 = rsp->data.regs.arm.ttbr1;
+
+    if ( psr_mode_is_32bit(regs->cpsr) )
+    {
+        regs->r0 = rsp->data.regs.arm.arch.arm32.r0_usr;
+        regs->r1 = rsp->data.regs.arm.arch.arm32.r1_usr;
+        regs->r2 = rsp->data.regs.arm.arch.arm32.r2_usr;
+        regs->r3 = rsp->data.regs.arm.arch.arm32.r3_usr;
+        regs->r4 = rsp->data.regs.arm.arch.arm32.r4_usr;
+        regs->r5 = rsp->data.regs.arm.arch.arm32.r5_usr;
+        regs->r6 = rsp->data.regs.arm.arch.arm32.r6_usr;
+        regs->r7 = rsp->data.regs.arm.arch.arm32.r7_usr;
+        regs->r8 = rsp->data.regs.arm.arch.arm32.r8_usr;
+        regs->r9 = rsp->data.regs.arm.arch.arm32.r9_usr;
+        regs->r10 = rsp->data.regs.arm.arch.arm32.r10_usr;
+        regs->r12 = rsp->data.regs.arm.arch.arm32.r12_usr;
+        regs->pc32 = rsp->data.regs.arm.arch.arm32.pc;
+        regs->fp = rsp->data.regs.arm.arch.arm32.fp;
+        regs->lr_usr = rsp->data.regs.arm.arch.arm32.lr_usr;
+        regs->sp_usr = rsp->data.regs.arm.arch.arm32.sp_usr;
+        regs->sp_svc = rsp->data.regs.arm.arch.arm32.sp_svc;
+        regs->spsr_svc = rsp->data.regs.arm.arch.arm32.spsr_svc;
+    }
+#ifdef CONFIG_ARM_64
+    else
+    {
+        regs->x0 = rsp->data.regs.arm.arch.arm64.x0;
+        regs->x1 = rsp->data.regs.arm.arch.arm64.x1;
+        regs->x2 = rsp->data.regs.arm.arch.arm64.x2;
+        regs->x3 = rsp->data.regs.arm.arch.arm64.x3;
+        regs->x4 = rsp->data.regs.arm.arch.arm64.x4;
+        regs->x5 = rsp->data.regs.arm.arch.arm64.x5;
+        regs->x6 = rsp->data.regs.arm.arch.arm64.x6;
+        regs->x7 = rsp->data.regs.arm.arch.arm64.x7;
+        regs->x8 = rsp->data.regs.arm.arch.arm64.x8;
+        regs->x9 = rsp->data.regs.arm.arch.arm64.x9;
+        regs->x10 = rsp->data.regs.arm.arch.arm64.x10;
+        regs->x16 = rsp->data.regs.arm.arch.arm64.x16;
+        regs->pc = rsp->data.regs.arm.arch.arm64.pc;
+        regs->sp_el0 = rsp->data.regs.arm.arch.arm64.sp_el0;
+        regs->sp_el1 = rsp->data.regs.arm.arch.arm64.sp_el1;
+        regs->fp = rsp->data.regs.arm.arch.arm64.fp;
+        regs->lr = rsp->data.regs.arm.arch.arm64.lr;
+        regs->spsr_svc = rsp->data.regs.arm.arch.arm64.spsr_el1;
+    }
+#endif
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/vm_event.h b/xen/include/asm-arm/vm_event.h
index a3fc4ce..a4922b3 100644
--- a/xen/include/asm-arm/vm_event.h
+++ b/xen/include/asm-arm/vm_event.h
@@ -48,15 +48,4 @@ void vm_event_register_write_resume(struct vcpu *v, vm_event_response_t *rsp)
     /* Not supported on ARM. */
 }
 
-static inline
-void vm_event_set_registers(struct vcpu *v, vm_event_response_t *rsp)
-{
-    /* Not supported on ARM. */
-}
-
-static inline void vm_event_fill_regs(vm_event_request_t *req)
-{
-    /* Not supported on ARM. */
-}
-
 #endif /* __ASM_ARM_VM_EVENT_H__ */
diff --git a/xen/include/asm-x86/vm_event.h b/xen/include/asm-x86/vm_event.h
index 026f42e..cf2077c 100644
--- a/xen/include/asm-x86/vm_event.h
+++ b/xen/include/asm-x86/vm_event.h
@@ -40,8 +40,4 @@ void vm_event_toggle_singlestep(struct domain *d, struct vcpu *v);
 
 void vm_event_register_write_resume(struct vcpu *v, vm_event_response_t *rsp);
 
-void vm_event_set_registers(struct vcpu *v, vm_event_response_t *rsp);
-
-void vm_event_fill_regs(vm_event_request_t *req);
-
 #endif /* __ASM_X86_VM_EVENT_H__ */
diff --git a/xen/include/public/vm_event.h b/xen/include/public/vm_event.h
index 3acf217..6ff7cc0 100644
--- a/xen/include/public/vm_event.h
+++ b/xen/include/public/vm_event.h
@@ -129,8 +129,8 @@
 #define VM_EVENT_X86_XCR0   3
 
 /*
- * Using a custom struct (not hvm_hw_cpu) so as to not fill
- * the vm_event ring buffer too quickly.
+ * Using custom vCPU structs (i.e. not hvm_hw_cpu) for both x86 and ARM
+ * so as to not fill the vm_event ring buffer too quickly.
  */
 struct vm_event_regs_x86 {
     uint64_t rax;
@@ -168,6 +168,59 @@ struct vm_event_regs_x86 {
     uint32_t _pad;
 };
 
+struct vm_event_regs_arm32 {
+    uint32_t r0_usr;
+    uint32_t r1_usr;
+    uint32_t r2_usr;
+    uint32_t r3_usr;
+    uint32_t r4_usr;
+    uint32_t r5_usr;
+    uint32_t r6_usr;
+    uint32_t r7_usr;
+    uint32_t r8_usr;
+    uint32_t r9_usr;
+    uint32_t r10_usr;
+    uint32_t r12_usr;
+    uint32_t lr_usr;
+    uint32_t fp;
+    uint32_t pc;
+    uint32_t sp_usr;
+    uint32_t sp_svc;
+    uint32_t spsr_svc;
+};
+
+struct vm_event_regs_arm64 {
+    uint64_t x0;
+    uint64_t x1;
+    uint64_t x2;
+    uint64_t x3;
+    uint64_t x4;
+    uint64_t x5;
+    uint64_t x6;
+    uint64_t x7;
+    uint64_t x8;
+    uint64_t x9;
+    uint64_t x10;
+    uint64_t x16;
+    uint64_t lr;
+    uint64_t fp;
+    uint64_t pc;
+    uint64_t sp_el0;
+    uint64_t sp_el1;
+    uint32_t spsr_el1;
+    uint32_t _pad;
+};
+
+struct vm_event_regs_arm {
+    uint32_t cpsr; /* PSR_MODE_BIT is set iff arm32 is used below */
+    uint64_t ttbr0;
+    uint64_t ttbr1;
+    union {
+        struct vm_event_regs_arm32 arm32;
+        struct vm_event_regs_arm64 arm64;
+    } arch;
+};
+
 /*
  * mem_access flag definitions
  *
@@ -256,6 +309,7 @@ typedef struct vm_event_st {
     union {
         union {
             struct vm_event_regs_x86 x86;
+            struct vm_event_regs_arm arm;
         } regs;
 
         struct vm_event_emul_read_data emul_read_data;
diff --git a/xen/include/xen/vm_event.h b/xen/include/xen/vm_event.h
index 89e6243..a5767ab 100644
--- a/xen/include/xen/vm_event.h
+++ b/xen/include/xen/vm_event.h
@@ -75,6 +75,9 @@ int vm_event_domctl(struct domain *d, xen_domctl_vm_event_op_t *vec,
 void vm_event_vcpu_pause(struct vcpu *v);
 void vm_event_vcpu_unpause(struct vcpu *v);
 
+void vm_event_fill_regs(vm_event_request_t *req);
+void vm_event_set_registers(struct vcpu *v, vm_event_response_t *rsp);
+
 /*
  * Monitor vm-events
  */
