From patchwork Wed Jun 8 08:59:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quan Xu X-Patchwork-Id: 9163743 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 45C0360467 for ; Wed, 8 Jun 2016 09:05:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 352D728363 for ; Wed, 8 Jun 2016 09:05:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2964228393; Wed, 8 Jun 2016 09:05:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6FD5328363 for ; Wed, 8 Jun 2016 09:05:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAZOq-0004EN-EO; Wed, 08 Jun 2016 09:03:44 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bAZOp-0004DM-AB for xen-devel@lists.xen.org; Wed, 08 Jun 2016 09:03:43 +0000 Received: from [193.109.254.147] by server-15.bemta-14.messagelabs.com id 69/2B-29877-E6FD7575; Wed, 08 Jun 2016 09:03:42 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRWlGSWpSXmKPExsVywNwkQjf3fni 4wbyN2hZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa0bX9d3sBUdjKqa8T2pg3GbfxcjJISRQKTGh sYENxJYQ4JU4smwGK4TtL7Fx3iYWiJoaiZ7zl9hBbDYBFYkZze/AbBEBaYlrny8zdjFycTALv GCUaGvpYQRJCAtYSrSt/w9mswioSrTNngS2gFfASeJOz2+oZQoSy76sZe5i5ODgBIpvPVYKsc tRYtvuJywTGHkXMDKsYlQvTi0qSy3SNdNLKspMzyjJTczM0TU0NNHLTS0uTkxPzUlMKtZLzs/ dxAgMBAYg2MH4d4LzIUZJDiYlUV5F9/BwIb6k/JTKjMTijPii0pzU4kOMMhwcShK8tfeAcoJF qempFWmZOcCQhElLcPAoifBKgaR5iwsSc4sz0yFSpxgVpcR5RUESAiCJjNI8uDZYHFxilJUS5 mUEOkSIpyC1KDezBFX+FaM4B6OSMG8YyBSezLwSuOmvgBYzAS1efgRscUkiQkqqgfGE5V0N/z jBFzv+/jPJmL7ppATvND/dg24fgxO7Ou449BR8jwva4rJ+r8erMy9Zu7X3fLwQcu/vH6/2PEv tZFtbZp7PJ47q+im9UD5UE+H6lUtKiekK96Y3nbsL57R2Mvbeu/Kr/qpu8u4PB98ucDXjawzo /hnC7TjrYVmXkPbummCTI10Pk5RYijMSDbWYi4oTATvb8rR+AgAA X-Env-Sender: quan.xu@intel.com X-Msg-Ref: server-9.tower-27.messagelabs.com!1465376607!46437496!8 X-Originating-IP: [192.55.52.88] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjg4ID0+IDM3NDcyNQ==\n X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 29565 invoked from network); 8 Jun 2016 09:03:41 -0000 Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by server-9.tower-27.messagelabs.com with SMTP; 8 Jun 2016 09:03:41 -0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 08 Jun 2016 02:03:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,438,1459839600"; d="scan'208";a="983223992" Received: from xen-commits.sh.intel.com ([10.239.82.178]) by fmsmga001.fm.intel.com with ESMTP; 08 Jun 2016 02:03:39 -0700 From: "Xu, Quan" To: xen-devel@lists.xen.org Date: Wed, 8 Jun 2016 16:59:02 +0800 Message-Id: <1465376344-28290-10-git-send-email-quan.xu@intel.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1465376344-28290-1-git-send-email-quan.xu@intel.com> References: <1465376344-28290-1-git-send-email-quan.xu@intel.com> Cc: Kevin Tian , Keir Fraser , Quan Xu , Andrew Cooper , dario.faggioli@citrix.com, Jan Beulich , Feng Wu Subject: [Xen-devel] [PATCH v7 09/11] vt-d: fix the IOMMU flush issue X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Quan Xu The propagation value from IOMMU flush interfaces may be positive, which indicates callers need to flush cache, not one of faliures. when the propagation value is positive, this patch fixes this flush issue as follows: - call iommu_flush_write_buffer() to flush cache. - return zero. Signed-off-by: Quan Xu Reviewed-by: Jan Beulich CC: Kevin Tian CC: Feng Wu CC: Keir Fraser CC: Jan Beulich CC: Andrew Cooper v7: 1. Drop blank lines. 2. make the assignment be replaced by its right side becoming the variable's initializer. 3. leave the comments as are, no reply from VT-d maintainers yet. --- xen/drivers/passthrough/vtd/iommu.c | 167 ++++++++++++++++++++++++++---------- 1 file changed, 124 insertions(+), 43 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index 48edb67..2a55985 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -388,17 +388,18 @@ static int flush_context_reg( return 0; } -static int iommu_flush_context_global( - struct iommu *iommu, int flush_non_present_entry) +static int __must_check iommu_flush_context_global(struct iommu *iommu, + int flush_non_present_entry) { struct iommu_flush *flush = iommu_get_flush(iommu); return flush->context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL, flush_non_present_entry); } -static int iommu_flush_context_device( - struct iommu *iommu, u16 did, u16 source_id, - u8 function_mask, int flush_non_present_entry) +static int __must_check iommu_flush_context_device(struct iommu *iommu, + u16 did, u16 source_id, + u8 function_mask, + int flush_non_present_entry) { struct iommu_flush *flush = iommu_get_flush(iommu); return flush->context(iommu, did, source_id, function_mask, @@ -473,8 +474,9 @@ static int flush_iotlb_reg(void *_iommu, u16 did, return 0; } -static int iommu_flush_iotlb_global(struct iommu *iommu, - int flush_non_present_entry, int flush_dev_iotlb) +static int __must_check iommu_flush_iotlb_global(struct iommu *iommu, + int flush_non_present_entry, + int flush_dev_iotlb) { struct iommu_flush *flush = iommu_get_flush(iommu); int status; @@ -491,8 +493,9 @@ static int iommu_flush_iotlb_global(struct iommu *iommu, return status; } -static int iommu_flush_iotlb_dsi(struct iommu *iommu, u16 did, - int flush_non_present_entry, int flush_dev_iotlb) +static int __must_check iommu_flush_iotlb_dsi(struct iommu *iommu, u16 did, + int flush_non_present_entry, + int flush_dev_iotlb) { struct iommu_flush *flush = iommu_get_flush(iommu); int status; @@ -509,9 +512,10 @@ static int iommu_flush_iotlb_dsi(struct iommu *iommu, u16 did, return status; } -static int iommu_flush_iotlb_psi( - struct iommu *iommu, u16 did, u64 addr, unsigned int order, - int flush_non_present_entry, int flush_dev_iotlb) +static int __must_check iommu_flush_iotlb_psi(struct iommu *iommu, u16 did, + u64 addr, unsigned int order, + int flush_non_present_entry, + int flush_dev_iotlb) { struct iommu_flush *flush = iommu_get_flush(iommu); int status; @@ -545,18 +549,42 @@ static int __must_check iommu_flush_all(void) { struct acpi_drhd_unit *drhd; struct iommu *iommu; - int flush_dev_iotlb; + int rc = 0; flush_all_cache(); for_each_drhd_unit ( drhd ) { iommu = drhd->iommu; - iommu_flush_context_global(iommu, 0); - flush_dev_iotlb = find_ats_dev_drhd(iommu) ? 1 : 0; - iommu_flush_iotlb_global(iommu, 0, flush_dev_iotlb); + /* + * The current logic for rc returns: + * - positive invoke iommu_flush_write_buffer to flush cache. + * - zero on success. + * - negative on failure. Continue to flush IOMMU IOTLB on a + * best effort basis. + * + * Moreover, IOMMU flush handlers flush_context_qi and flush_iotlb_qi + * (or flush_context_reg and flush_iotlb_reg, deep functions in the + * call trees of iommu_flush_context_global and iommu_flush_iotlb_global) + * are with the same logic to bubble up positive return value. + */ + rc = iommu_flush_context_global(iommu, 0); + if ( rc <= 0 ) + { + int flush_dev_iotlb = find_ats_dev_drhd(iommu) ? 1 : 0; + int ret = iommu_flush_iotlb_global(iommu, 0, flush_dev_iotlb); + + ASSERT(ret <= 0); + if ( !rc ) + rc = ret; + } + else + { + iommu_flush_write_buffer(iommu); + rc = 0; + } } - return 0; + return rc; } static int __must_check iommu_flush_iotlb(struct domain *d, @@ -569,6 +597,7 @@ static int __must_check iommu_flush_iotlb(struct domain *d, struct iommu *iommu; int flush_dev_iotlb; int iommu_domid; + int rc = 0; /* * No need pcideves_lock here because we have flush @@ -587,21 +616,23 @@ static int __must_check iommu_flush_iotlb(struct domain *d, continue; if ( page_count != 1 || gfn == INVALID_GFN ) - { - if ( iommu_flush_iotlb_dsi(iommu, iommu_domid, - 0, flush_dev_iotlb) ) - iommu_flush_write_buffer(iommu); - } + rc = iommu_flush_iotlb_dsi(iommu, iommu_domid, + 0, flush_dev_iotlb); else + rc = iommu_flush_iotlb_psi(iommu, iommu_domid, + (paddr_t)gfn << PAGE_SHIFT_4K, + PAGE_ORDER_4K, + !dma_old_pte_present, + flush_dev_iotlb); + + if ( rc > 0 ) { - if ( iommu_flush_iotlb_psi(iommu, iommu_domid, - (paddr_t)gfn << PAGE_SHIFT_4K, PAGE_ORDER_4K, - !dma_old_pte_present, flush_dev_iotlb) ) - iommu_flush_write_buffer(iommu); + iommu_flush_write_buffer(iommu); + rc = 0; } } - return 0; + return rc; } static int __must_check iommu_flush_iotlb_pages(struct domain *d, @@ -1291,6 +1322,7 @@ int domain_context_mapping_one( u64 maddr, pgd_maddr; u16 seg = iommu->intel->drhd->segment; int agaw; + int rc; ASSERT(pcidevs_locked()); spin_lock(&iommu->lock); @@ -1404,13 +1436,34 @@ int domain_context_mapping_one( spin_unlock(&iommu->lock); /* Context entry was previously non-present (with domid 0). */ - if ( iommu_flush_context_device(iommu, 0, (((u16)bus) << 8) | devfn, - DMA_CCMD_MASK_NOBIT, 1) ) - iommu_flush_write_buffer(iommu); - else + rc = iommu_flush_context_device(iommu, 0, PCI_BDF2(bus, devfn), + DMA_CCMD_MASK_NOBIT, 1); + + /* + * The current logic for rc returns: + * - positive invoke iommu_flush_write_buffer to flush cache. + * - zero on success. + * - negative on failure. Continue to flush IOMMU IOTLB on a + * best effort basis. + * + * Moreover, IOMMU flush handlers flush_context_qi or flush_iotlb_qi + * (or flush_context_reg and flush_iotlb_reg, deep functions in the + * call trees of iommu_flush_context_device and iommu_flush_iotlb_dsi) + * are with the same logic to bubble up positive return value. + */ + if ( rc <= 0 ) { int flush_dev_iotlb = find_ats_dev_drhd(iommu) ? 1 : 0; - iommu_flush_iotlb_dsi(iommu, 0, 1, flush_dev_iotlb); + int ret = iommu_flush_iotlb_dsi(iommu, 0, 1, flush_dev_iotlb); + + ASSERT(ret <= 0); + if ( !rc ) + rc = ret; + } + else + { + iommu_flush_write_buffer(iommu); + rc = 0; } set_bit(iommu->index, &hd->arch.iommu_bitmap); @@ -1420,7 +1473,7 @@ int domain_context_mapping_one( if ( !seg ) me_wifi_quirk(domain, bus, devfn, MAP_ME_PHANTOM_FUNC); - return 0; + return rc; } static int domain_context_mapping( @@ -1515,6 +1568,7 @@ int domain_context_unmap_one( struct context_entry *context, *context_entries; u64 maddr; int iommu_domid; + int rc; ASSERT(pcidevs_locked()); spin_lock(&iommu->lock); @@ -1542,14 +1596,35 @@ int domain_context_unmap_one( return -EINVAL; } - if ( iommu_flush_context_device(iommu, iommu_domid, - (((u16)bus) << 8) | devfn, - DMA_CCMD_MASK_NOBIT, 0) ) - iommu_flush_write_buffer(iommu); - else + rc = iommu_flush_context_device(iommu, iommu_domid, + PCI_BDF2(bus, devfn), + DMA_CCMD_MASK_NOBIT, 0); + + /* + * The current logic for rc returns: + * - positive invoke iommu_flush_write_buffer to flush cache. + * - zero on success. + * - negative on failure. Continue to flush IOMMU IOTLB on a + * best effort basis. + * + * Moreover, IOMMU flush handlers flush_context_qi or flush_iotlb_qi + * (or flush_context_reg and flush_iotlb_reg, deep functions in the + * call trees of iommu_flush_context_device and iommu_flush_iotlb_dsi) + * are with the same logic to bubble up positive return value. + */ + if ( rc <= 0 ) { int flush_dev_iotlb = find_ats_dev_drhd(iommu) ? 1 : 0; - iommu_flush_iotlb_dsi(iommu, iommu_domid, 0, flush_dev_iotlb); + int ret = iommu_flush_iotlb_dsi(iommu, iommu_domid, 0, flush_dev_iotlb); + + ASSERT(ret <= 0); + if ( !rc ) + rc = ret; + } + else + { + iommu_flush_write_buffer(iommu); + rc = 0; } spin_unlock(&iommu->lock); @@ -1558,7 +1633,7 @@ int domain_context_unmap_one( if ( !iommu->intel->drhd->segment ) me_wifi_quirk(domain, bus, devfn, UNMAP_ME_PHANTOM_FUNC); - return 0; + return rc; } static int domain_context_unmap( @@ -1772,6 +1847,7 @@ int iommu_pte_flush(struct domain *d, u64 gfn, u64 *pte, struct domain_iommu *hd = dom_iommu(d); int flush_dev_iotlb; int iommu_domid; + int rc = 0; iommu_flush_cache_entry(pte, sizeof(struct dma_pte)); @@ -1785,13 +1861,18 @@ int iommu_pte_flush(struct domain *d, u64 gfn, u64 *pte, iommu_domid= domain_iommu_domid(d, iommu); if ( iommu_domid == -1 ) continue; - if ( iommu_flush_iotlb_psi(iommu, iommu_domid, + + rc = iommu_flush_iotlb_psi(iommu, iommu_domid, (paddr_t)gfn << PAGE_SHIFT_4K, - order, !present, flush_dev_iotlb) ) + order, !present, flush_dev_iotlb); + if ( rc > 0 ) + { iommu_flush_write_buffer(iommu); + rc = 0; + } } - return 0; + return rc; } static int __init vtd_ept_page_compatible(struct iommu *iommu)