| Message ID | 1465467250-8742-3-git-send-email-euan.harris@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 09.06.16 at 12:14, <euan.harris@citrix.com> wrote: > --- a/xen/arch/x86/hvm/vmx/vvmx.c > +++ b/xen/arch/x86/hvm/vmx/vvmx.c > @@ -1820,11 +1820,20 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) > return 0; > > /* > - * Those MSRs are available only when bit 55 of > - * MSR_IA32_VMX_BASIC is set. > + * These MSRs are only available when flags in other MSRs are set. > + * These prerequisites are listed in the Intel 64 and IA-32 > + * Architectures Software Developer’s Manual, Vol 3, Appendix A. > */ > - switch ( msr ) > - { > + switch ( msr ) { case MSR_IA32_VMX_PROCBASED_CTLS2: I hope you didn't really mean to produce a garbled line like this? With proper formatting restored Reviewed-by: Jan Beulich <jbeulich@suse.com>
On Thu, Jun 09, 2016 at 06:47:55AM -0600, Jan Beulich wrote: > > /* > > - * Those MSRs are available only when bit 55 of > > - * MSR_IA32_VMX_BASIC is set. > > + * These MSRs are only available when flags in other MSRs are set. > > + * These prerequisites are listed in the Intel 64 and IA-32 > > + * Architectures Software Developer’s Manual, Vol 3, Appendix A. > > */ > > - switch ( msr ) > > - { > > + switch ( msr ) { case MSR_IA32_VMX_PROCBASED_CTLS2: > > I hope you didn't really mean to produce a garbled line like this? > With proper formatting restored > Reviewed-by: Jan Beulich <jbeulich@suse.com> Oops, definitely not. I think this happened when I was re-wrapping the comment above - !}fmt went further than I intended. Sorry, Euan
> From: Euan Harris [mailto:euan.harris@citrix.com] > Sent: Thursday, June 09, 2016 9:21 PM > > On Thu, Jun 09, 2016 at 06:47:55AM -0600, Jan Beulich wrote: > > > /* > > > - * Those MSRs are available only when bit 55 of > > > - * MSR_IA32_VMX_BASIC is set. > > > + * These MSRs are only available when flags in other MSRs are set. > > > + * These prerequisites are listed in the Intel 64 and IA-32 > > > + * Architectures Software Developer’s Manual, Vol 3, Appendix A. > > > */ > > > - switch ( msr ) > > > - { > > > + switch ( msr ) { case MSR_IA32_VMX_PROCBASED_CTLS2: > > > > I hope you didn't really mean to produce a garbled line like this? > > With proper formatting restored > > Reviewed-by: Jan Beulich <jbeulich@suse.com> > > Oops, definitely not. I think this happened when I was re-wrapping > the comment above - !}fmt went further than I intended. > Acked-by: Kevin Tian <kevin.tian@intel.com>, with above fixed.
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index d9493ff..ddc25bf 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1820,11 +1820,20 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) return 0; /* - * Those MSRs are available only when bit 55 of - * MSR_IA32_VMX_BASIC is set. + * These MSRs are only available when flags in other MSRs are set. + * These prerequisites are listed in the Intel 64 and IA-32 + * Architectures Software Developer’s Manual, Vol 3, Appendix A. */ - switch ( msr ) - { + switch ( msr ) { case MSR_IA32_VMX_PROCBASED_CTLS2: + if ( !cpu_has_vmx_secondary_exec_control ) + return 0; + break; + + case MSR_IA32_VMX_EPT_VPID_CAP: + if ( !(cpu_has_vmx_ept || cpu_has_vmx_vpid) ) + return 0; + break; + case MSR_IA32_VMX_TRUE_PINBASED_CTLS: case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: case MSR_IA32_VMX_TRUE_EXIT_CTLS: @@ -1832,6 +1841,11 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) if ( !(vmx_basic_msr & VMX_BASIC_DEFAULT1_ZERO) ) return 0; break; + + case MSR_IA32_VMX_VMFUNC: + if ( !cpu_has_vmx_vmfunc ) + return 0; + break; } rdmsrl(msr, host_data);
Some VMX MSRs may not exist on certain processor models, or may be disabled because of configuration settings. It is only safe to access these MSRs if configuration flags in other MSRs are set. These prerequisites are listed in the Intel 64 and IA-32 Architectures Software Developer’s Manual, Vol 3, Appendix A. nvmx_msr_read_intercept() does not check the prerequisites before accessing MSR_IA32_VMX_PROCBASED_CTLS2, MSR_IA32_VMX_EPT_VPID_CAP, MSR_IA32_VMX_VMFUNC on the host. Accessing these MSRs from a nested VMX guest running on a host which does not support them will cause Xen to crash with a GPF. Signed-off-by: Euan Harris <euan.harris@citrix.com> --- xen/arch/x86/hvm/vmx/vvmx.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-)