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Tue, 21 Jun 2016 11:16:13 +0200 Received: from hi-z08if.hi.de.bosch.com (localhost [127.0.0.1]) by hi-z08if.hi.de.bosch.com (Postfix) with ESMTP id 67FF4625F16; Tue, 21 Jun 2016 11:15:30 +0200 (CEST) From: Dirk Behme To: , Julien Grall , Stefano Stabellini Date: Tue, 21 Jun 2016 11:15:28 +0200 Message-ID: <1466500528-8411-3-git-send-email-dirk.behme@de.bosch.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1466500528-8411-1-git-send-email-dirk.behme@de.bosch.com> References: <1466500528-8411-1-git-send-email-dirk.behme@de.bosch.com> MIME-Version: 1.0 X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-8.0.0.1202-22402.006 X-TMASE-MatchedRID: gefcZ1WzChc/pUoYqyfnNAPZZctd3P4B7f6JAS2hKPgbFebmbVBKrqg/ vmRELCWbsddWSH8bQq6XMrecyIcRv4QHE7x6AHFuaDCzqDR7DPYK3iJpXUOQQ7uqk4cq52pztlo lH3QPrXbi8zVgXoAltsIJ+4gwXrEtIAcCikR3vq8YytQdzIicD5oMsv1ec1Jckbozm/DWUO5C25 3CMQnPsDGIyz0staPx Cc: Oleksandr Tyshchenko , Iurii Konovalenko , Dirk Behme Subject: [Xen-devel] [PATCH 3/3] xen/arm: drivers: scif: Add clock auto detection X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Besides the 14MHz external clock, the SCIF might be clocked by an internal 66MHz clock. Detect this clock based on the SCIF_DL register being 0 (internal clock) or != 0 (external clock). Signed-off-by: Dirk Behme --- xen/drivers/char/scif-uart.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index bc157fe..678f46b 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -107,8 +107,19 @@ static void __init scif_uart_init_preirq(struct serial_port *port) scif_readw(uart, SCIF_SCLSR); scif_writew(uart, SCIF_SCLSR, 0); - /* Select Baud rate generator output as a clock source */ - scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10); + /* + * Select Baud rate generator output as a clock source + * The clock source can be an internal or external clock. + * Depending on this the DL register is either 0 or contains + * the divisor. I.e. we can use this to detect the clock + * source and based on this can configure the CKE[1:0] bits + * of the SCSCR register. + */ + if ( scif_readw(uart, SCIF_DL) ) + scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10); /* External clk */ + else + scif_writew(uart, SCIF_SCSCR, SCSCR_CKE00); /* Internal clk */ + /* Setup protocol format and Baud rate, select Asynchronous mode */ val = 0;