From patchwork Fri Jun 24 05:51:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quan Xu X-Patchwork-Id: 9196683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4A70E6075F for ; Fri, 24 Jun 2016 05:59:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3AE1A283EB for ; Fri, 24 Jun 2016 05:59:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E99128490; Fri, 24 Jun 2016 05:59:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9AC2F283EB for ; Fri, 24 Jun 2016 05:59:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bGK6l-00082r-M2; Fri, 24 Jun 2016 05:56:51 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bGK6j-00081p-Hu for xen-devel@lists.xen.org; Fri, 24 Jun 2016 05:56:49 +0000 Received: from [85.158.137.68] by server-12.bemta-3.messagelabs.com id 3F/21-32245-0ABCC675; Fri, 24 Jun 2016 05:56:48 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLLMWRWlGSWpSXmKPExsXS1tYhobvgdE6 4wb77shZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8a5K9OZCiYoVHza0MvSwLhDrIuRk0NIoFLi 393XTCC2hACvxJFlM1ghbH+JCSfWMEPU1Ejs+rcOrIZNQEViRvM7dhBbREBa4trny4xdjFwcz ALzGSVeProLlhAWiJa4fGQBWAOLgKrE1eMPgWwODl4BR4nXkxUh5itILPuyFmw+p4CTxKtrm6 B2OUp8/NjIOoGRdwEjwypGjeLUorLUIl1DC72kosz0jJLcxMwcXUMDY73c1OLixPTUnMSkYr3 k/NxNjMBgqGdgYNzB+Pu05yFGSQ4mJVHeaYtywoX4kvJTKjMSizPii0pzUosPMcpwcChJ8B48 BZQTLEpNT61Iy8wBhiVMWoKDR0mElxMYmkK8xQWJucWZ6RCpU4yKUuIQfQIgiYzSPLg2WCxcY pSVEuZlZGBgEOIpSC3KzSxBlX/FKM7BqCTMewFkCk9mXgnc9FdAi5mAFt/tzwZZXJKIkJJqYG yR7deS6wp0TF84X+jk7MT9vnLJQR/5XmXeiCv/4XB291atheU3bUPvne1gZr6zaq7nJ7H0U2s nujLuLXhn9Gf5vOMLutZnrKp7fmuK7cWaw7vMTys+Wxdp/D+2U1yS7XLwI+/SBYrsZzs7LdOV Vn+fdmqi6Y5g/w8HpXI4Xgtvs91csMGDyUaJpTgj0VCLuag4EQAC1CrngAIAAA== X-Env-Sender: quan.xu@intel.com X-Msg-Ref: server-3.tower-31.messagelabs.com!1466747805!46915777!3 X-Originating-IP: [134.134.136.24] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjQgPT4gMzkwOTcx\n X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 18014 invoked from network); 24 Jun 2016 05:56:48 -0000 Received: from mga09.intel.com (HELO mga09.intel.com) (134.134.136.24) by server-3.tower-31.messagelabs.com with SMTP; 24 Jun 2016 05:56:48 -0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 23 Jun 2016 22:56:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,518,1459839600"; d="scan'208";a="127718719" Received: from xen-commits.sh.intel.com ([10.239.82.178]) by fmsmga004.fm.intel.com with ESMTP; 23 Jun 2016 22:56:45 -0700 From: "Xu, Quan" To: xen-devel@lists.xen.org Date: Fri, 24 Jun 2016 13:51:55 +0800 Message-Id: <1466747518-54402-4-git-send-email-quan.xu@intel.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1466747518-54402-1-git-send-email-quan.xu@intel.com> References: <1466747518-54402-1-git-send-email-quan.xu@intel.com> Cc: Kevin Tian , dario.faggioli@citrix.com, Feng Wu , Jan Beulich , Quan Xu Subject: [Xen-devel] [PATCH v12 3/6] vt-d: convert conditionals of qi_ctrl->qinval_maddr into ASSERT()s X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Quan Xu QI ought to have got disabled if any of the IOMMU table setup failed. A QI function (other than enable_qinval) is unreachable when qi_ctrl->qinval_maddr is zero. Signed-off-by: Quan Xu CC: Jan Beulich CC: Kevin Tian CC: Feng Wu Acked-by: Kevin Tian --- xen/drivers/passthrough/vtd/qinval.c | 52 ++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/xen/drivers/passthrough/vtd/qinval.c b/xen/drivers/passthrough/vtd/qinval.c index 46c4c8f..4492b29 100644 --- a/xen/drivers/passthrough/vtd/qinval.c +++ b/xen/drivers/passthrough/vtd/qinval.c @@ -204,10 +204,9 @@ static int __must_check invalidate_sync(struct iommu *iommu, { struct qi_ctrl *qi_ctrl = iommu_qi_ctrl(iommu); - if ( qi_ctrl->qinval_maddr ) - return queue_invalidate_wait(iommu, 0, 1, 1, flush_dev_iotlb); + ASSERT(qi_ctrl->qinval_maddr); - return 0; + return queue_invalidate_wait(iommu, 0, 1, 1, flush_dev_iotlb); } int qinval_device_iotlb_sync(struct iommu *iommu, @@ -297,10 +296,11 @@ static int __must_check flush_context_qi(void *_iommu, u16 did, u16 sid, u8 fm, u64 type, bool_t flush_non_present_entry) { - int ret = 0; struct iommu *iommu = (struct iommu *)_iommu; struct qi_ctrl *qi_ctrl = iommu_qi_ctrl(iommu); + ASSERT(qi_ctrl->qinval_maddr); + /* * In the non-present entry flush case, if hardware doesn't cache * non-present entry we do nothing and if hardware cache non-present @@ -315,11 +315,8 @@ static int __must_check flush_context_qi(void *_iommu, u16 did, did = 0; } - if ( qi_ctrl->qinval_maddr != 0 ) - ret = queue_invalidate_context_sync(iommu, did, sid, fm, - type >> DMA_CCMD_INVL_GRANU_OFFSET); - - return ret; + return queue_invalidate_context_sync(iommu, did, sid, fm, + type >> DMA_CCMD_INVL_GRANU_OFFSET); } static int __must_check flush_iotlb_qi(void *_iommu, u16 did, u64 addr, @@ -328,10 +325,12 @@ static int __must_check flush_iotlb_qi(void *_iommu, u16 did, u64 addr, bool_t flush_dev_iotlb) { u8 dr = 0, dw = 0; - int ret = 0; + int ret = 0, rc; struct iommu *iommu = (struct iommu *)_iommu; struct qi_ctrl *qi_ctrl = iommu_qi_ctrl(iommu); + ASSERT(qi_ctrl->qinval_maddr); + /* * In the non-present entry flush case, if hardware doesn't cache * non-present entry we do nothing and if hardware cache non-present @@ -346,28 +345,23 @@ static int __must_check flush_iotlb_qi(void *_iommu, u16 did, u64 addr, did = 0; } - if ( qi_ctrl->qinval_maddr != 0 ) + /* use queued invalidation */ + if (cap_write_drain(iommu->cap)) + dw = 1; + if (cap_read_drain(iommu->cap)) + dr = 1; + /* Need to conside the ih bit later */ + rc = queue_invalidate_iotlb_sync(iommu, + type >> DMA_TLB_FLUSH_GRANU_OFFSET, + dr, dw, did, size_order, 0, addr); + if ( !ret ) + ret = rc; + + if ( flush_dev_iotlb ) { - int rc; - - /* use queued invalidation */ - if (cap_write_drain(iommu->cap)) - dw = 1; - if (cap_read_drain(iommu->cap)) - dr = 1; - /* Need to conside the ih bit later */ - rc = queue_invalidate_iotlb_sync(iommu, - type >> DMA_TLB_FLUSH_GRANU_OFFSET, - dr, dw, did, size_order, 0, addr); + rc = dev_invalidate_iotlb(iommu, did, addr, size_order, type); if ( !ret ) ret = rc; - - if ( flush_dev_iotlb ) - { - rc = dev_invalidate_iotlb(iommu, did, addr, size_order, type); - if ( !ret ) - ret = rc; - } } return ret; }