From patchwork Tue Jun 28 08:12:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kai Huang X-Patchwork-Id: 9202265 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0291060757 for ; Tue, 28 Jun 2016 08:15:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E7935285E7 for ; Tue, 28 Jun 2016 08:15:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DC68F285F5; Tue, 28 Jun 2016 08:15:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1D73C285E7 for ; Tue, 28 Jun 2016 08:14:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bHo8h-0005xG-5W; Tue, 28 Jun 2016 08:12:59 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bHo8g-0005x7-01 for xen-devel@lists.xen.org; Tue, 28 Jun 2016 08:12:58 +0000 Received: from [85.158.143.35] by server-1.bemta-6.messagelabs.com id E6/F5-09256-98132775; Tue, 28 Jun 2016 08:12:57 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJIsWRWlGSWpSXmKPExsVyMfSOo26HYVG 4QdcCPYslHxezODB6HN39mymAMYo1My8pvyKBNWNiXzdTwSbLiu4zU1kaGO/rdjFycQgJTGCU +LHsJUsXIycHi8AlFomr06NBEhIC71gk7jQfZgJJSAjESEx9tooRwq6SOPnuOTOILSSgLNH17 Sg7xKRuJolb876zgiTYBKQk3ix5ww7RYCgx4WIHmC0ikCRx9PQbsG3MApoSy9eeAYsLC/hJHH +4mhXiClWJb9c/gNm8Ah4STbsWsEDMkZO4ea6TeQIj/wJGhlWM6sWpRWWpRbqGeklFmekZJbm JmTm6hgZmermpxcWJ6ak5iUnFesn5uZsYgQHEAAQ7GHc+dzrEKMnBpCTKu4ChKFyILyk/pTIj sTgjvqg0J7X4EKMMB4eSBK+iAVBOsCg1PbUiLTMHGMowaQkOHiUR3liQNG9xQWJucWY6ROoUo zHHlt/X1jJxbJt6by2TEEtefl6qlDhvJEipAEhpRmke3CBYjF1ilJUS5mUEOk2IpyC1KDezBF X+FaM4B6OSMK8VyBSezLwSuH2vgE5hAjqFtTof5JSSRISUVAOj+rPE7fq8hYGdZisc1PRUeGV /avwqWnxvsimnx53KZLWpYsd+d+5/+qFx1/pYw5bVAbesj/1ntYrgFZor4WrPqfjb9IBxn+9a fxUxS+lvyhFrxHkM/RaWyWV9k3xZnvw+vj4mf/LGHRXnp7qcUjpi/ktmF5vonbP9aXMfrFlY9 Z1T9Y1k/iQlluKMREMt5qLiRAAKyWvfrAIAAA== X-Env-Sender: kaih.linux@gmail.com X-Msg-Ref: server-8.tower-21.messagelabs.com!1467101575!21146999!1 X-Originating-IP: [209.85.220.65] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 54378 invoked from network); 28 Jun 2016 08:12:56 -0000 Received: from mail-pa0-f65.google.com (HELO mail-pa0-f65.google.com) (209.85.220.65) by server-8.tower-21.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 28 Jun 2016 08:12:56 -0000 Received: by mail-pa0-f65.google.com with SMTP id hf6so1060660pac.2 for ; Tue, 28 Jun 2016 01:12:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=JDFTvXBXWx/ZcMZiZSP+D0PwevKOkDfmmFTBP7lRhfw=; b=Y7j2yMmGFjpv27FFs2TOvnGjeXtdb1lXHMwxC/4Hbd82FHrlEWZDNY/sP5b4ffFz65 QUZ6tS4h0ncoIiEuboKDPkD/yjn2DWxgGKxNrThPv/NJxQkEt1aVQ8s5IWCsMSSBj/5k YpW5Xtht9MA8Q6yW94opGc0uBC89tmqW+mNAlTy+gGa/9p3ABPcUvw2Bp4VTkPYyiWjk bZsSXjxo2LTTfFnLCRNr7fQowQbjz/bK98k/hasORXvpzRWvUaq0CdI3JgiK9pBo9uUt DD7wmRrAyJvVl1JwNf9NIKqTUaETfuNg68PnkipnkcTkBKaQ9c6K9uou+/baM73zyONI e+tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=JDFTvXBXWx/ZcMZiZSP+D0PwevKOkDfmmFTBP7lRhfw=; b=CObnjyHoGjc+K8QlXHkpDWER6HhP1v4xid1VzHBlA6oXvfxMfHBueArJOQdcdo1ELq JgKAt7RaCjith08HymUJKbdp6NvqduJgWS343LkbCAMvQQz9NK75MBC1UvVRjS/1o+nW 9ysCLdBD/2rQocdYgK6yd5o6QDJPYm53+7fN9n9ljK0FLaxKMyJF7DiVHMQygi2Nee1L X9wDZYprz7NlVGzynGF9XKrZ56uTu6fD2TaXsdvBoivSdAOKWmtedEO1GjpIcYjl84Cm 1TdN62dcTJQgbn3WePQogdI0u907l3dMfQu94WuyXZHf3GBO5R92SDsTPJgrv6DalwwW kbyw== X-Gm-Message-State: ALyK8tLh8YTdxuFPg3vjm1ZHAwjcK50e/uVkp9Fb2nwcddVOYOF4rZ0tAHiK+QY3dO8SwQ== X-Received: by 10.66.178.49 with SMTP id cv17mr2656392pac.157.1467101574815; Tue, 28 Jun 2016 01:12:54 -0700 (PDT) Received: from kai-ubuntu.fritz.box ([2406:e007:fd9:1:e4d2:9b81:63b5:de5e]) by smtp.gmail.com with ESMTPSA id 6sm5413228pfs.29.2016.06.28.01.12.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Jun 2016 01:12:54 -0700 (PDT) From: kaih.linux@gmail.com X-Google-Original-From: kai.huang@linux.intel.com To: jbeulich@suse.com, kevin.tian@intel.com, andrew.cooper3@citrix.com, xen-devel@lists.xen.org Date: Tue, 28 Jun 2016 20:12:48 +1200 Message-Id: <1467101568-2842-1-git-send-email-kai.huang@linux.intel.com> X-Mailer: git-send-email 2.7.4 Cc: Kai Huang Subject: [Xen-devel] [PATCH v2] xen: x86: remove duplicated IA32_FEATURE_CONTROL MSR macro X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Kai Huang Below commit introduced a new macro MSR_IA32_FEATURE_CONTROL for IA32_FEATURE_CONTROL MSR but it didn't remove old IA32_FEATURE_CONTROL_MSR macro. The new one has better naming convention, so remove the old as a duplication. Also move the macros of bit definition of IA32_FEATURE_CONTROL MSR down to make them together with the new one. The *_MSR* infix is also removed as it is pointless. commit 5a211704e8813c4890c8ce8dc4189d1dfb35ecd0 Author: Len Brown Date: Fri Apr 8 22:31:47 2016 +0200 mwait-idle: prevent SKL-H boot failure when C8+C9+C10 enabled Some SKL-H configurations require "max_cstate=7" to boot. While that is an effective workaround, it disables C10. ...... Above commit also used SGX_ENABLE (bit 18) in IA32_FEATURE_CONTROL MSR without a macro for it. A new macro IA32_FEATURE_CONTROL_SGX_ENABLE is also added for better code and future use. Relevant code that uses those macros are changed accordingly. Signed-off-by: Kai Huang Reviewed-by: Jan Beulich Acked-by: Kevin Tian --- v1 -> v2: Moved the macros for bit definition of IA32_FEATURE_CONTROL MSR down to make them together with the MSR macro. Removed the *_MSR* infix. Also refined commit message. --- xen/arch/x86/cpu/mwait-idle.c | 2 +- xen/arch/x86/hvm/vmx/vmcs.c | 20 ++++++++++---------- xen/arch/x86/hvm/vmx/vmx.c | 4 ++-- xen/arch/x86/hvm/vmx/vvmx.c | 6 +++--- xen/include/asm-x86/msr-index.h | 14 ++++++++------ 5 files changed, 24 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index e062e21..4b33974 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1006,7 +1006,7 @@ static void __init sklh_idle_state_table_update(void) rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); /* if SGX is enabled */ - if (msr & (1 << 18)) + if (msr & IA32_FEATURE_CONTROL_SGX_ENABLE) return; } diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 848ac33..46b63b6 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -604,14 +604,14 @@ int vmx_cpu_up(void) return -EINVAL; } - rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx); + rdmsr(MSR_IA32_FEATURE_CONTROL, eax, edx); - bios_locked = !!(eax & IA32_FEATURE_CONTROL_MSR_LOCK); + bios_locked = !!(eax & IA32_FEATURE_CONTROL_LOCK); if ( bios_locked ) { if ( !(eax & (tboot_in_measured_env() - ? IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX - : IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX)) ) + ? IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX + : IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX)) ) { printk("CPU%d: VMX disabled by BIOS.\n", cpu); return -EINVAL; @@ -619,11 +619,11 @@ int vmx_cpu_up(void) } else { - eax = IA32_FEATURE_CONTROL_MSR_LOCK; - eax |= IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX; + eax = IA32_FEATURE_CONTROL_LOCK; + eax |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; if ( test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) ) - eax |= IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX; - wrmsr(IA32_FEATURE_CONTROL_MSR, eax, 0); + eax |= IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX; + wrmsr(MSR_IA32_FEATURE_CONTROL, eax, 0); } if ( (rc = vmx_init_vmcs_config()) != 0 ) @@ -639,8 +639,8 @@ int vmx_cpu_up(void) case -2: /* #UD or #GP */ if ( bios_locked && test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) && - (!(eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX) || - !(eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX)) ) + (!(eax & IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX) || + !(eax & IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX)) ) { printk("CPU%d: VMXON failed: perhaps because of TXT settings " "in your BIOS configuration?\n", cpu); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 54cdb86..c23b1e9 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2622,7 +2622,7 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) case MSR_IA32_DEBUGCTLMSR: __vmread(GUEST_IA32_DEBUGCTL, msr_content); break; - case IA32_FEATURE_CONTROL_MSR: + case MSR_IA32_FEATURE_CONTROL: case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_VMFUNC: if ( !nvmx_msr_read_intercept(msr, msr_content) ) goto gp_fault; @@ -2848,7 +2848,7 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) break; } - case IA32_FEATURE_CONTROL_MSR: + case MSR_IA32_FEATURE_CONTROL: case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS: if ( !nvmx_msr_write_intercept(msr, msr_content) ) goto gp_fault; diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index c6a39e9..bed2e0a 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1941,9 +1941,9 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) data = gen_vmx_msr(data, VMX_ENTRY_CTLS_DEFAULT1, host_data); break; - case IA32_FEATURE_CONTROL_MSR: - data = IA32_FEATURE_CONTROL_MSR_LOCK | - IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX; + case MSR_IA32_FEATURE_CONTROL: + data = IA32_FEATURE_CONTROL_LOCK | + IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; break; case MSR_IA32_VMX_VMCS_ENUM: /* The max index of VVMCS encoding is 0x1f. */ diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index e0f7f8d..6098f13 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -133,12 +133,6 @@ #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 #define MSR_IA32_VMX_VMFUNC 0x491 -#define IA32_FEATURE_CONTROL_MSR 0x3a -#define IA32_FEATURE_CONTROL_MSR_LOCK 0x0001 -#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX 0x0002 -#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004 -#define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL 0x7f00 -#define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER 0x8000 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */ @@ -288,7 +282,15 @@ #define MSR_IA32_PLATFORM_ID 0x00000017 #define MSR_IA32_EBL_CR_POWERON 0x0000002a #define MSR_IA32_EBC_FREQUENCY_ID 0x0000002c + #define MSR_IA32_FEATURE_CONTROL 0x0000003a +#define IA32_FEATURE_CONTROL_LOCK 0x0001 +#define IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX 0x0002 +#define IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX 0x0004 +#define IA32_FEATURE_CONTROL_SENTER_PARAM_CTL 0x7f00 +#define IA32_FEATURE_CONTROL_ENABLE_SENTER 0x8000 +#define IA32_FEATURE_CONTROL_SGX_ENABLE 0x40000 + #define MSR_IA32_TSC_ADJUST 0x0000003b #define MSR_IA32_APICBASE 0x0000001b