From patchwork Thu Jul 14 16:21:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 9230139 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9548A6075D for ; Thu, 14 Jul 2016 16:25:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 85C0927FA4 for ; Thu, 14 Jul 2016 16:25:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 795AC28285; Thu, 14 Jul 2016 16:25:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CBC3127FA4 for ; Thu, 14 Jul 2016 16:25:07 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bNjPT-0003vt-R1; Thu, 14 Jul 2016 16:22:47 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bNjPS-0003vR-TZ for xen-devel@lists.xen.org; Thu, 14 Jul 2016 16:22:47 +0000 Received: from [85.158.137.68] by server-8.bemta-3.messagelabs.com id E7/A0-03780-65CB7875; Thu, 14 Jul 2016 16:22:46 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTTd0T3u 4weLJkhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8afj4fYCjYZVTyesIupgXGyehcjF4eQwCZG ia+Pf7BDOKcZJTZ/+MfSxcjJwSagKXHn8ycmEFtEQFri2ufLjCA2s0ChxPWzT9hAbGEBO4mZp /axgtgsAqoSc86uAarh4OAVcJF4eVINJCwhICdx8thksBJOAVeJFbs/gbUKAZXMfXqTeQIj9w JGhlWMGsWpRWWpRbpGBnpJRZnpGSW5iZk5uoYGxnq5qcXFiempOYlJxXrJ+bmbGIH+rWdgYNz B2HzC7xCjJAeTkiivdn9buBBfUn5KZUZicUZ8UWlOavEhRhkODiUJ3r7d7eFCgkWp6akVaZk5 wECDSUtw8CiJ8E4GSfMWFyTmFmemQ6ROMSpKifPGgSQEQBIZpXlwbbDgvsQoKyXMy8jAwCDEU 5BalJtZgir/ilGcg1FJmDcHZApPZl4J3PRXQIuZgBZbm4MtLklESEk1ME7a7e8f9ICndNLfUu ONzq6tJr6rgyNTsmXPiUr/kuTMEexm/cyuVp/F/eH5QU0f43lSfn9yU50Kzp63PLb38+8Xon8 jLp86dTfPvtrMT6rqyK5Fz9rF/Tme9nJ+2l0odr9tu1bB/x0Js2/WNZoVN9RbPb7POmmWoNCE Ha1ZrvbMQSpxVe4/lViKMxINtZiLihMBDhUoDWkCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-6.tower-31.messagelabs.com!1468513364!24380898!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 34397 invoked from network); 14 Jul 2016 16:22:45 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-6.tower-31.messagelabs.com with SMTP; 14 Jul 2016 16:22:45 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1621F3A1; Thu, 14 Jul 2016 09:23:20 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8640F3F4F6; Thu, 14 Jul 2016 09:22:13 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Jul 2016 17:21:59 +0100 Message-Id: <1468513325-29492-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468513325-29492-1-git-send-email-julien.grall@arm.com> References: <1468513325-29492-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, shankerd@codeaurora.org, steve.capper@arm.com Subject: [Xen-devel] [PATCH v2 3/9] xen/arm: gic: split set_irq_properties X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The callback set_irq_properties will configure the GIC for a specific IRQ with the type and the priority. In a follow-up patch, Xen will configure the type and the priority at different stage of the routing. So split it in 2 separate callbacks. At the same time, move the ASSERT to check the validity of the type and if the desc->lock is locked in the common code (gic.c). This is because the constraint are the same between GICv2 and GICv3, however the driver of the latter did not contain any sanity check. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Stefano's reviewed-by --- xen/arch/arm/gic-v2.c | 19 +++++++++++++------ xen/arch/arm/gic-v3.c | 15 ++++++++++++--- xen/arch/arm/gic.c | 23 ++++++++++++++--------- xen/include/asm-arm/gic.h | 7 ++++--- 4 files changed, 43 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 6c7dbfe..69ed72d 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -236,16 +236,12 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } -static void gicv2_set_irq_properties(struct irq_desc *desc, - unsigned int priority) +static void gicv2_set_irq_type(struct irq_desc *desc) { uint32_t cfg, actual, edgebit; unsigned int irq = desc->irq; unsigned int type = desc->arch.type; - ASSERT(type != IRQ_TYPE_INVALID); - ASSERT(spin_is_locked(&desc->lock)); - spin_lock(&gicv2.lock); /* Set edge / level */ cfg = readl_gicd(GICD_ICFGR + (irq / 16) * 4); @@ -270,6 +266,16 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_LEVEL_HIGH; } + spin_unlock(&gicv2.lock); +} + +static void gicv2_set_irq_priority(struct irq_desc *desc, + unsigned int priority) +{ + unsigned int irq = desc->irq; + + spin_lock(&gicv2.lock); + /* Set priority */ writeb_gicd(priority, GICD_IPRIORITYR + irq); @@ -1217,7 +1223,8 @@ const static struct gic_hw_operations gicv2_ops = { .eoi_irq = gicv2_eoi_irq, .deactivate_irq = gicv2_dir_irq, .read_irq = gicv2_read_irq, - .set_irq_properties = gicv2_set_irq_properties, + .set_irq_type = gicv2_set_irq_type, + .set_irq_priority = gicv2_set_irq_priority, .send_SGI = gicv2_send_SGI, .disable_interface = gicv2_disable_interface, .update_lr = gicv2_update_lr, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index d6ab0e9..781f25c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -471,8 +471,7 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu) MPIDR_AFFINITY_LEVEL(mpidr, 0)); } -static void gicv3_set_irq_properties(struct irq_desc *desc, - unsigned int priority) +static void gicv3_set_irq_type(struct irq_desc *desc) { uint32_t cfg, actual, edgebit; void __iomem *base; @@ -512,6 +511,15 @@ static void gicv3_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_EDGE_RISING : IRQ_TYPE_LEVEL_HIGH; } + spin_unlock(&gicv3.lock); +} + +static void gicv3_set_irq_priority(struct irq_desc *desc, + unsigned int priority) +{ + unsigned int irq = desc->irq; + + spin_lock(&gicv3.lock); /* Set priority */ if ( irq < NR_GIC_LOCAL_IRQS ) @@ -1579,7 +1587,8 @@ static const struct gic_hw_operations gicv3_ops = { .eoi_irq = gicv3_eoi_irq, .deactivate_irq = gicv3_dir_irq, .read_irq = gicv3_read_irq, - .set_irq_properties = gicv3_set_irq_properties, + .set_irq_type = gicv3_set_irq_type, + .set_irq_priority = gicv3_set_irq_priority, .send_SGI = gicv3_send_sgi, .disable_interface = gicv3_disable_interface, .update_lr = gicv3_update_lr, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index bc814a0..c63c862 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -96,14 +96,17 @@ void gic_restore_state(struct vcpu *v) gic_restore_pending_irqs(v); } -/* - * - desc.lock must be held - * - arch.type must be valid (i.e != IRQ_TYPE_INVALID) - */ -static void gic_set_irq_properties(struct irq_desc *desc, - unsigned int priority) +static void gic_set_irq_type(struct irq_desc *desc) +{ + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(desc->arch.type != IRQ_TYPE_INVALID); + + gic_hw_ops->set_irq_type(desc); +} + +static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority) { - gic_hw_ops->set_irq_properties(desc, priority); + gic_hw_ops->set_irq_priority(desc, priority); } /* Program the GIC to route an interrupt to the host (i.e. Xen) @@ -118,7 +121,8 @@ void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) desc->handler = gic_hw_ops->gic_host_irq_type; - gic_set_irq_properties(desc, priority); + gic_set_irq_type(desc); + gic_set_irq_priority(desc, priority); } /* Program the GIC to route an interrupt to a guest @@ -150,7 +154,8 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, desc->handler = gic_hw_ops->gic_guest_irq_type; set_bit(_IRQ_GUEST, &desc->status); - gic_set_irq_properties(desc, priority); + gic_set_irq_type(desc); + gic_set_irq_priority(desc, priority); p->desc = desc; res = 0; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 7ba3846..3f39f79 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -328,9 +328,10 @@ struct gic_hw_operations { void (*deactivate_irq)(struct irq_desc *irqd); /* Read IRQ id and Ack */ unsigned int (*read_irq)(void); - /* Set IRQ property */ - void (*set_irq_properties)(struct irq_desc *desc, - unsigned int priority); + /* Set IRQ type - type is taken from desc->arch.type */ + void (*set_irq_type)(struct irq_desc *desc); + /* Set IRQ priority */ + void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority); /* Send SGI */ void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode, const cpumask_t *online_mask);