From patchwork Tue Aug 23 01:54:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luwei Kang X-Patchwork-Id: 9294873 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D8D08607D0 for ; Tue, 23 Aug 2016 01:57:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C884128AFE for ; Tue, 23 Aug 2016 01:57:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BCE2A28B4A; Tue, 23 Aug 2016 01:57:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0FC1E28AFE for ; Tue, 23 Aug 2016 01:57:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bc0vo-0006ff-Nf; Tue, 23 Aug 2016 01:55:12 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bc0vn-0006fZ-Kq for xen-devel@lists.xen.org; Tue, 23 Aug 2016 01:55:11 +0000 Received: from [85.158.139.211] by server-16.bemta-5.messagelabs.com id 40/27-26103-EFCABB75; Tue, 23 Aug 2016 01:55:10 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRWlGSWpSXmKPExsVywNykWPffmt3 hBif/CVks+biYxYHR4+ju30wBjFGsmXlJ+RUJrBlnnq9jLFhmUnF/KmcD4xXVLkZODiGBCok7 26ewgNgSArwSR5bNYIWwAyR2XG5ih6ipkvh19DkbiM0moC6x9f1GsBoRAWmJa58vM3YxcnEwC 3QzSix+8R3I4eAQFrCQWHsrAaSGRUBVYmrvC0YQm1fAReLDqd1Q8+Ukbp7rZJ7AyL2AkWEVo0 ZxalFZapGukaVeUlFmekZJbmJmjq6hgalebmpxcWJ6ak5iUrFecn7uJkagb+sZGBh3MF7e4ne IUZKDSUmU96/z7nAhvqT8lMqMxOKM+KLSnNTiQ4wyHBxKErz5wFAREixKTU+tSMvMAQYZTFqC g0dJhLcZJM1bXJCYW5yZDpE6xagoJc7rA5IQAElklObBtcEC+xKjrJQwLyMDA4MQT0FqUW5mC ar8K0ZxDkYlYd4ekCk8mXklcNNfAS1mAlp8/f92kMUliQgpqQbGiICmtLdzdrHu3vVi97KbHB XcO5c7KYZFX9R8dXKHp2tpu0ahXJ/sBPajh2NXCzypDdi7K3v5zmUvbL4WV0WtvXLR2Sd/q+f z6izGgzyuOgafmsyf7vpyMuq77q4b/gwnDbZUOHVYqVRskDr8x156Xc+hqx/5a5Z01R9/tVog T57VNblStjxeiaU4I9FQi7moOBEARDA4v2cCAAA= X-Env-Sender: luwei.kang@intel.com X-Msg-Ref: server-5.tower-206.messagelabs.com!1471917307!54095118!1 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 8.84; banners=-,-,- X-VirusChecked: Checked Received: (qmail 65383 invoked from network); 23 Aug 2016 01:55:09 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-5.tower-206.messagelabs.com with DHE-RSA-CAMELLIA256-SHA encrypted SMTP; 23 Aug 2016 01:55:09 -0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 22 Aug 2016 18:55:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,563,1464678000"; d="scan'208"; a="1039937167" Received: from vmm-dell.bj.intel.com ([10.238.154.151]) by orsmga002.jf.intel.com with ESMTP; 22 Aug 2016 18:55:06 -0700 From: Luwei Kang To: xen-devel@lists.xen.org Date: Tue, 23 Aug 2016 09:54:24 +0800 Message-Id: <1471917264-13607-1-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 2.7.4 Cc: andrew.cooper3@citrix.com, Luwei Kang , yong.y.wang@intel.com, jbeulich@suse.com, chao.p.peng@linux.intel.com Subject: [Xen-devel] [PATCH v5] x86/cpuid: AVX-512 Feature Detection X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP AVX512 is an extention of AVX2. Its spec can be found at: https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf This patch detects AVX512 features by CPUID. Signed-off-by: Luwei Kang Reviewed-by: Jan Beulich Reviewed-by: Andrew Cooper --- [V5]: Modify the comment of dependency between AVX512 and AVX2. [V4]: Update the description about features dependency. [V3]: Adjust dependencies between features. [V2]: 1.get max xstate_size from each bit. 2.change get cpuid function parameter from 0x07 to 7. 3.add dependencies between features in xen/tools/gen-cpuid.py. 4.split the cpuid call just like the way the hvm_cpuid() side works. --- xen/arch/x86/hvm/hvm.c | 14 ++++++++++++++ xen/arch/x86/traps.c | 22 +++++++++++++++++++++- xen/include/public/arch-x86/cpufeatureset.h | 9 +++++++++ xen/tools/gen-cpuid.py | 10 ++++++++++ 4 files changed, 54 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 7f99087..edea87e 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3472,6 +3472,20 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, xstate_sizes[_XSTATE_BNDCSR]); } + if ( _ebx & cpufeat_mask(X86_FEATURE_AVX512F) ) + { + xfeature_mask |= XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM; + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_OPMASK] + + xstate_sizes[_XSTATE_OPMASK]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_ZMM] + + xstate_sizes[_XSTATE_ZMM]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_HI_ZMM] + + xstate_sizes[_XSTATE_HI_ZMM]); + } + if ( _ecx & cpufeat_mask(X86_FEATURE_PKU) ) { xfeature_mask |= XSTATE_PKRU; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 767d0b0..8fb697b 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -975,7 +975,7 @@ void pv_cpuid(struct cpu_user_regs *regs) switch ( leaf ) { - uint32_t tmp, _ecx; + uint32_t tmp, _ecx, _ebx; case 0x00000001: c &= pv_featureset[FEATURESET_1c]; @@ -1157,6 +1157,26 @@ void pv_cpuid(struct cpu_user_regs *regs) xstate_sizes[_XSTATE_YMM]); } + if ( !is_control_domain(currd) && !is_hardware_domain(currd) ) + domain_cpuid(currd, 7, 0, &tmp, &_ebx, &tmp, &tmp); + else + cpuid_count(7, 0, &tmp, &_ebx, &tmp, &tmp); + _ebx &= pv_featureset[FEATURESET_7b0]; + + if ( _ebx & cpufeat_mask(X86_FEATURE_AVX512F) ) + { + xfeature_mask |= XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM; + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_OPMASK] + + xstate_sizes[_XSTATE_OPMASK]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_ZMM] + + xstate_sizes[_XSTATE_ZMM]); + xstate_size = max(xstate_size, + xstate_offsets[_XSTATE_HI_ZMM] + + xstate_sizes[_XSTATE_HI_ZMM]); + } + a = (uint32_t)xfeature_mask; d = (uint32_t)(xfeature_mask >> 32); c = xstate_size; diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 39acf8c..9320c9e 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -206,15 +206,24 @@ XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ XEN_CPUFEATURE(MPX, 5*32+14) /*S Memory Protection Extensions */ XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ +XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */ +XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */ XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ +XEN_CPUFEATURE(AVX512IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */ XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ +XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */ +XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */ +XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */ XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ +XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */ +XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ +XEN_CPUFEATURE(AVX512VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */ XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 7c45eca..0229d2c 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -243,6 +243,16 @@ def crunch_numbers(state): # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. _3DNOW: [_3DNOWEXT], + + # This is just the dependency between AVX512 and AVX2 of XSTATE feature flags. + # If want to use AVX512, AVX2 must be supported and enabled. + AVX2: [AVX512F], + + # AVX512F is taken to mean hardware support for EVEX encoded instructions, + # 512bit registers, and the instructions themselves. All further AVX512 features + # are built on top of AVX512F + AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD, + AVX512BW, AVX512VL, AVX512VBMI], } deep_features = tuple(sorted(deps.keys()))