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Wed, 21 Sep 2016 10:33:04 -0700 From: Konrad Rzeszutek Wilk To: konrad@kernel.org, xen-devel@lists.xenproject.org, ross.lagerwall@citrix.com, sstabellini@kernel.org, julien.grall@arm.com Date: Wed, 21 Sep 2016 13:32:30 -0400 Message-Id: <1474479154-20991-13-git-send-email-konrad.wilk@oracle.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1474479154-20991-1-git-send-email-konrad.wilk@oracle.com> References: <1474479154-20991-1-git-send-email-konrad.wilk@oracle.com> X-Source-IP: userv0021.oracle.com [156.151.31.71] Cc: Konrad Rzeszutek Wilk Subject: [Xen-devel] [PATCH v5 12/16] xen/arm32: Add an helper to invalidate all instruction caches X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This is similar to commit fb9d877a9c0f3d4d15db8f6e0c5506ea641862c6 "xen/arm64: Add an helper to invalidate all instruction caches" except it is on ARM32 side. When we are flushing the cache we are most likley also want to flush the branch predictor too. Hence we add this. And we also need to follow this with dsb()/isb() which are memory barriers(). Signed-off-by: Konrad Rzeszutek Wilk Reviewed-by: Julien Grall --- Cc: Julien Grall Cc: Stefano Stabellini v2: First submission v3: Squashed "xen/arm32/livepatch: Add BPICALLIS to helper to invalidate all instruction caches" in this patch. v4: Added dsb()/isb() instructions. --- xen/include/asm-arm/arm32/page.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index bccdbfc..ea4b312 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -30,6 +30,22 @@ static inline void write_pte(lpae_t *p, lpae_t pte) #define __clean_and_invalidate_dcache_one(R) STORE_CP32(R, DCCIMVAC) /* + * Invalidate all instruction caches in Inner Shareable domain to PoU. + * We also need to flush the branch predictor for ARMv7 as it may be + * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b). + */ +static inline void invalidate_icache(void) +{ + asm volatile ( + CMD_CP32(ICIALLUIS) /* Flush I-cache. */ + CMD_CP32(BPIALLIS) /* Flush branch predictor. */ + : : : "memory"); + + dsb(ish); /* Ensure completion of the flush I-cache */ + isb(); /* Synchronize fetched instruction stream. */ +} + +/* * Flush all hypervisor mappings from the TLB and branch predictor of * the local processor. *