From patchwork Tue Sep 27 15:57:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 9352185 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0D7D860757 for ; Tue, 27 Sep 2016 16:00:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F2D442927A for ; Tue, 27 Sep 2016 16:00:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E76EA2928F; Tue, 27 Sep 2016 16:00:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 333172927A for ; Tue, 27 Sep 2016 16:00:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1boumF-0008Cm-Fm; Tue, 27 Sep 2016 15:58:39 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1boumD-00087c-SX for xen-devel@lists.xenproject.org; Tue, 27 Sep 2016 15:58:37 +0000 Received: from [85.158.139.211] by server-5.bemta-5.messagelabs.com id 4B/82-30284-D279AE75; Tue, 27 Sep 2016 15:58:37 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRWlGSWpSXmKPExsXitHRDpK7O9Ff hBj3t6hbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8b1k48ZCx5HVvy+18rUwLjPpYuRk0NCwF/i yIlVzCA2m4COxMW5O9m6GDk4RARUJG7vNehi5OJgFrjBKPH7UyNYjbCAm8Taha/ZQGwWAVWJY xN62UFsXgFXiRcftrJAzNSVeHjuNyuIzQkU721bwARiCwm4SNyd+ZEVol5Q4uTMJ2D1zAKaEq 3bf7ND2PISzVtnM0PUK0r0z3vABjGTW+L26anMExj5ZyFpn4WkfRaS9gWMzKsY1YtTi8pSi3R N9ZKKMtMzSnITM3N0DQ1M9XJTi4sT01NzEpOK9ZLzczcxAkOQAQh2MH7pdz7EKMnBpCTKq9H+ KlyILyk/pTIjsTgjvqg0J7X4EKMGB4fA5rWrLzBKseTl56UqSfB6TAWqEyxKTU+tSMvMAUYJT KkEB4+SCC/PNKA0b3FBYm5xZjpE6hSjopQ4bwNInwBIIqM0D64NFpmXGGWlhHkZgY4S4ilILc rNLEGVf8UozsGoJMyrADKeJzOvBG76K6DFTECLl554AbK4JBEhJdXAyHqfVVzM6+z39wuON+5 s1rDlbTk0QTSUx7/3H8ODotbekCjhB8d37W56P6t8f/vP35OmPlBaoWR89MqSh7fU3sfsTtde /WGnhDzT2/m/Sk64nFp4Zaub6vdYLUPRa8mPM/8emPk9ZO3scNf+Y+vyd5SdDtnIx81j2v7qm cXGpfPlFDpvGli1cSixFGckGmoxFxUnAgC3hGsYxwIAAA== X-Env-Sender: prvs=071b8e69e=roger.pau@citrix.com X-Msg-Ref: server-11.tower-206.messagelabs.com!1474991912!49616454!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 8.84; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8751 invoked from network); 27 Sep 2016 15:58:35 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-11.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 27 Sep 2016 15:58:35 -0000 X-IronPort-AV: E=Sophos;i="5.30,405,1470700800"; d="scan'208";a="380934524" From: Roger Pau Monne To: Date: Tue, 27 Sep 2016 17:57:18 +0200 Message-ID: <1474991845-27962-24-git-send-email-roger.pau@citrix.com> X-Mailer: git-send-email 2.7.4 (Apple Git-66) In-Reply-To: <1474991845-27962-1-git-send-email-roger.pau@citrix.com> References: <1474991845-27962-1-git-send-email-roger.pau@citrix.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: Andrew Cooper , Paul Durrant , Jan Beulich , boris.ostrovsky@oracle.com, Roger Pau Monne Subject: [Xen-devel] [PATCH v2 23/30] xen/x86: route legacy PCI interrupts to Dom0 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This is done adding some Dom0 specific logic to the IO APIC emulation inside of Xen, so that writes to the IO APIC registers that should unmask an interrupt will take care of setting up this interrupt with Xen. A Dom0 specific EIO handler also has to be used, since Xen doesn't know the topology of the PCI devices and it just has to passthrough what Dom0 does. Signed-off-by: Roger Pau Monné --- Cc: Jan Beulich Cc: Andrew Cooper Cc: Paul Durrant --- xen/arch/x86/hvm/irq.c | 9 +++ xen/arch/x86/hvm/vioapic.c | 28 ++++++++- xen/arch/x86/physdev.c | 4 -- xen/drivers/passthrough/io.c | 144 ++++++++++++++++++++++++++++++++++++++----- xen/include/asm-x86/hvm/io.h | 2 + xen/include/asm-x86/irq.h | 5 ++ xen/include/xen/hvm/irq.h | 3 + xen/include/xen/iommu.h | 1 + 8 files changed, 177 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c index 5323d7c..be9b648 100644 --- a/xen/arch/x86/hvm/irq.c +++ b/xen/arch/x86/hvm/irq.c @@ -88,6 +88,15 @@ void hvm_pci_intx_assert( spin_unlock(&d->arch.hvm_domain.irq_lock); } +void hvm_hw_gsi_assert(struct domain *d, unsigned int gsi) +{ + + ASSERT(is_hardware_domain(d)); + spin_lock(&d->arch.hvm_domain.irq_lock); + assert_gsi(d, gsi); + spin_unlock(&d->arch.hvm_domain.irq_lock); +} + static void __hvm_pci_intx_deassert( struct domain *d, unsigned int device, unsigned int intx) { diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c index 611be87..18305be 100644 --- a/xen/arch/x86/hvm/vioapic.c +++ b/xen/arch/x86/hvm/vioapic.c @@ -148,6 +148,29 @@ static void vioapic_write_redirent( unmasked = unmasked && !ent.fields.mask; } + if ( is_hardware_domain(d) && unmasked ) + { + int ret, gsi; + + /* Interrupt has been unmasked */ + gsi = idx; + ret = mp_register_gsi(gsi, ent.fields.trig_mode, ent.fields.polarity); + if ( ret && ret != -EEXIST ) + { + gdprintk(XENLOG_WARNING, + "%s: error registering GSI %d\n", __func__, ret); + } + if ( !ret ) + { + ret = physdev_map_pirq(DOMID_SELF, MAP_PIRQ_TYPE_GSI, &gsi, &gsi, + NULL); + BUG_ON(ret); + + ret = pt_irq_bind_hw_domain(gsi); + BUG_ON(ret); + } + } + *pent = ent; if ( idx == 0 ) @@ -409,7 +432,10 @@ void vioapic_update_EOI(struct domain *d, u8 vector) if ( iommu_enabled ) { spin_unlock(&d->arch.hvm_domain.irq_lock); - hvm_dpci_eoi(d, gsi, ent); + if ( is_hardware_domain(d) ) + hvm_hw_dpci_eoi(d, gsi, ent); + else + hvm_dpci_eoi(d, gsi, ent); spin_lock(&d->arch.hvm_domain.irq_lock); } diff --git a/xen/arch/x86/physdev.c b/xen/arch/x86/physdev.c index 0bea6e1..27dcbf4 100644 --- a/xen/arch/x86/physdev.c +++ b/xen/arch/x86/physdev.c @@ -19,10 +19,6 @@ #include #include -int physdev_map_pirq(domid_t, int type, int *index, int *pirq_p, - struct msi_info *); -int physdev_unmap_pirq(domid_t, int pirq); - #include "x86_64/mmconfig.h" #ifndef COMPAT diff --git a/xen/drivers/passthrough/io.c b/xen/drivers/passthrough/io.c index 66577b6..edd8dbd 100644 --- a/xen/drivers/passthrough/io.c +++ b/xen/drivers/passthrough/io.c @@ -159,26 +159,29 @@ static int pt_irq_guest_eoi(struct domain *d, struct hvm_pirq_dpci *pirq_dpci, static void pt_irq_time_out(void *data) { struct hvm_pirq_dpci *irq_map = data; - const struct hvm_irq_dpci *dpci; const struct dev_intx_gsi_link *digl; spin_lock(&irq_map->dom->event_lock); - dpci = domain_get_irq_dpci(irq_map->dom); - ASSERT(dpci); - list_for_each_entry ( digl, &irq_map->digl_list, list ) + if ( !is_hardware_domain(irq_map->dom) ) { - unsigned int guest_gsi = hvm_pci_intx_gsi(digl->device, digl->intx); - const struct hvm_girq_dpci_mapping *girq; - - list_for_each_entry ( girq, &dpci->girq[guest_gsi], list ) + const struct hvm_irq_dpci *dpci = domain_get_irq_dpci(irq_map->dom); + ASSERT(dpci); + list_for_each_entry ( digl, &irq_map->digl_list, list ) { - struct pirq *pirq = pirq_info(irq_map->dom, girq->machine_gsi); + unsigned int guest_gsi = hvm_pci_intx_gsi(digl->device, digl->intx); + const struct hvm_girq_dpci_mapping *girq; + + list_for_each_entry ( girq, &dpci->girq[guest_gsi], list ) + { + struct pirq *pirq = pirq_info(irq_map->dom, girq->machine_gsi); - pirq_dpci(pirq)->flags |= HVM_IRQ_DPCI_EOI_LATCH; + pirq_dpci(pirq)->flags |= HVM_IRQ_DPCI_EOI_LATCH; + } + hvm_pci_intx_deassert(irq_map->dom, digl->device, digl->intx); } - hvm_pci_intx_deassert(irq_map->dom, digl->device, digl->intx); - } + } else + irq_map->flags |= HVM_IRQ_DPCI_EOI_LATCH; pt_pirq_iterate(irq_map->dom, pt_irq_guest_eoi, NULL); @@ -557,6 +560,85 @@ int pt_irq_create_bind( return 0; } +int pt_irq_bind_hw_domain(int gsi) +{ + struct domain *d = hardware_domain; + struct hvm_pirq_dpci *pirq_dpci; + struct hvm_irq_dpci *hvm_irq_dpci; + struct pirq *info; + int rc; + + if ( gsi < 0 || gsi >= d->nr_pirqs ) + return -EINVAL; + +restart: + spin_lock(&d->event_lock); + + hvm_irq_dpci = domain_get_irq_dpci(d); + if ( hvm_irq_dpci == NULL ) + { + unsigned int i; + + hvm_irq_dpci = xzalloc(struct hvm_irq_dpci); + if ( hvm_irq_dpci == NULL ) + { + spin_unlock(&d->event_lock); + return -ENOMEM; + } + for ( i = 0; i < NR_HVM_IRQS; i++ ) + INIT_LIST_HEAD(&hvm_irq_dpci->girq[i]); + + d->arch.hvm_domain.irq.dpci = hvm_irq_dpci; + } + + info = pirq_get_info(d, gsi); + if ( !info ) + { + spin_unlock(&d->event_lock); + return -ENOMEM; + } + pirq_dpci = pirq_dpci(info); + + /* + * A crude 'while' loop with us dropping the spinlock and giving + * the softirq_dpci a chance to run. + * We MUST check for this condition as the softirq could be scheduled + * and hasn't run yet. Note that this code replaced tasklet_kill which + * would have spun forever and would do the same thing (wait to flush out + * outstanding hvm_dirq_assist calls. + */ + if ( pt_pirq_softirq_active(pirq_dpci) ) + { + spin_unlock(&d->event_lock); + cpu_relax(); + goto restart; + } + + pirq_dpci->dom = d; + pirq_dpci->flags = HVM_IRQ_DPCI_MAPPED | + HVM_IRQ_DPCI_MACH_PCI | + HVM_IRQ_DPCI_GUEST_PCI; + + /* Init timer before binding */ + if ( pt_irq_need_timer(pirq_dpci->flags) ) + init_timer(&pirq_dpci->timer, pt_irq_time_out, pirq_dpci, 0); + + rc = pirq_guest_bind(d->vcpu[0], info, gsi > 15 ? BIND_PIRQ__WILL_SHARE : + 0); + if ( unlikely(rc) ) + { + if ( pt_irq_need_timer(pirq_dpci->flags) ) + kill_timer(&pirq_dpci->timer); + pirq_dpci->dom = NULL; + pirq_cleanup_check(info, d); + spin_unlock(&d->event_lock); + return rc; + } + + spin_unlock(&d->event_lock); + return 0; +} + int pt_irq_destroy_bind( struct domain *d, xen_domctl_bind_pt_irq_t *pt_irq_bind) { @@ -819,11 +901,19 @@ static void hvm_dirq_assist(struct domain *d, struct hvm_pirq_dpci *pirq_dpci) return; } - list_for_each_entry ( digl, &pirq_dpci->digl_list, list ) + if ( is_hardware_domain(d) ) { - hvm_pci_intx_assert(d, digl->device, digl->intx); + hvm_hw_gsi_assert(d, pirq->pirq); pirq_dpci->pending++; } + else + { + list_for_each_entry ( digl, &pirq_dpci->digl_list, list ) + { + hvm_pci_intx_assert(d, digl->device, digl->intx); + pirq_dpci->pending++; + } + } if ( pirq_dpci->flags & HVM_IRQ_DPCI_TRANSLATE ) { @@ -899,6 +989,32 @@ unlock: spin_unlock(&d->event_lock); } +void hvm_hw_dpci_eoi(struct domain *d, unsigned int gsi, + const union vioapic_redir_entry *ent) +{ + struct pirq *pirq = pirq_info(d, gsi); + struct hvm_pirq_dpci *pirq_dpci; + + ASSERT(is_hardware_domain(d) && iommu_enabled); + + if ( pirq == NULL ) + return; + + pirq_dpci = pirq_dpci(pirq); + ASSERT(pirq_dpci != NULL); + + spin_lock(&d->event_lock); + if ( --pirq_dpci->pending || (ent && ent->fields.mask) || + !pt_irq_need_timer(pirq_dpci->flags) ) + goto unlock; + + stop_timer(&pirq_dpci->timer); + pirq_guest_eoi(pirq); + +unlock: + spin_unlock(&d->event_lock); +} + /* * Note: 'pt_pirq_softirq_reset' can clear the STATE_SCHED before we get to * doing it. If that is the case we let 'pt_pirq_softirq_reset' do ref-counting. diff --git a/xen/include/asm-x86/hvm/io.h b/xen/include/asm-x86/hvm/io.h index 25af036..bfd76ff 100644 --- a/xen/include/asm-x86/hvm/io.h +++ b/xen/include/asm-x86/hvm/io.h @@ -126,6 +126,8 @@ int handle_pio(uint16_t port, unsigned int size, int dir); void hvm_interrupt_post(struct vcpu *v, int vector, int type); void hvm_dpci_eoi(struct domain *d, unsigned int guest_irq, const union vioapic_redir_entry *ent); +void hvm_hw_dpci_eoi(struct domain *d, unsigned int gsi, + const union vioapic_redir_entry *ent); void msix_write_completion(struct vcpu *); void msixtbl_init(struct domain *d); diff --git a/xen/include/asm-x86/irq.h b/xen/include/asm-x86/irq.h index 7efdd37..07f21ab 100644 --- a/xen/include/asm-x86/irq.h +++ b/xen/include/asm-x86/irq.h @@ -201,4 +201,9 @@ bool_t cpu_has_pending_apic_eoi(void); static inline void arch_move_irqs(struct vcpu *v) { } +struct msi_info; +int physdev_map_pirq(domid_t, int type, int *index, int *pirq_p, + struct msi_info *); +int physdev_unmap_pirq(domid_t, int pirq); + #endif /* _ASM_HW_IRQ_H */ diff --git a/xen/include/xen/hvm/irq.h b/xen/include/xen/hvm/irq.h index 4c9cb20..2ffaf35 100644 --- a/xen/include/xen/hvm/irq.h +++ b/xen/include/xen/hvm/irq.h @@ -122,6 +122,9 @@ void hvm_isa_irq_assert( void hvm_isa_irq_deassert( struct domain *d, unsigned int isa_irq); +/* Modify state of a hardware domain GSI */ +void hvm_hw_gsi_assert(struct domain *d, unsigned int gsi); + void hvm_set_pci_link_route(struct domain *d, u8 link, u8 isa_irq); int hvm_inject_msi(struct domain *d, uint64_t addr, uint32_t data); diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 5803e3f..07c6c40 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -114,6 +114,7 @@ struct pirq; int hvm_do_IRQ_dpci(struct domain *, struct pirq *); int pt_irq_create_bind(struct domain *, xen_domctl_bind_pt_irq_t *); int pt_irq_destroy_bind(struct domain *, xen_domctl_bind_pt_irq_t *); +int pt_irq_bind_hw_domain(int gsi); void hvm_dpci_isairq_eoi(struct domain *d, unsigned int isairq); struct hvm_irq_dpci *domain_get_irq_dpci(const struct domain *);