From patchwork Tue Oct 25 03:40:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9393909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 67CD760762 for ; Tue, 25 Oct 2016 02:37:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A42F28EE5 for ; Tue, 25 Oct 2016 02:37:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4EAB329296; Tue, 25 Oct 2016 02:37:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6F9C42927D for ; Tue, 25 Oct 2016 02:37:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byrYb-0004FF-GV; Tue, 25 Oct 2016 02:33:41 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1byrYa-0004F1-OO for xen-devel@lists.xenproject.org; Tue, 25 Oct 2016 02:33:40 +0000 Received: from [193.109.254.147] by server-2.bemta-6.messagelabs.com id 54/66-26478-484CE085; Tue, 25 Oct 2016 02:33:40 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKIsWRWlGSWpSXmKPExsVywNykWLf5CF+ EwcSTTBbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8bhtTfYCrbGV3xovMTUwLjDpYuRk0NIoEJi WtciVhBbQoBX4siyGVB2gMSykw+Zuxi5gGoaGCX+bXnACJJgE1CXePy1hwnEFhFQkri3ajITS BGzwH5GiV8vH7OAJIQFwiR+bFoCNolFQFWi9e8JdhCbV8BdYuK652wQG+QkTh6bDFbDKeAhcW fvcXaIi9wl+hqaGCHqBSVOznwCNJMDaIG6xPp5QiBhZgF5ieats5knMArMQlI1C6FqFpKqBYz Mqxg1ilOLylKLdA3N9ZKKMtMzSnITM3N0DQ3M9HJTi4sT01NzEpOK9ZLzczcxAoOTAQh2MN7e GHCIUZKDSUmUd+YmvgghvqT8lMqMxOKM+KLSnNTiQ4wyHBxKErzrDwPlBItS01Mr0jJzgHECk 5bg4FES4X0CkuYtLkjMLc5Mh0idYlSUEuddBJIQAElklObBtcFi8xKjrJQwLyPQIUI8BalFuZ klqPKvGMU5GJWEeV+ATOHJzCuBm/4KaDET0GLBeB6QxSWJCCmpBkaLyxcDVovYWf67dUT49a7 U51PvHxfbw6mV0XNpPfs5rVyzKSXO7I3lkdIKn+q2JVZnzwpn4Fcy+X8r+bmoonGGxfsFCyNO 89Wv2O1j1HLmz+nfc81cms6eWL/3m/fsy1bCMw5tSTzpl38+WdZPs+aSoPY8R/m19jNeaiR/S jg02bWynXPLv6dKLMUZiYZazEXFiQBOmiPOyAIAAA== X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1477362814!54875270!2 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.0.13; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48997 invoked from network); 25 Oct 2016 02:33:38 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-14.tower-27.messagelabs.com with DHE-RSA-CAMELLIA256-SHA encrypted SMTP; 25 Oct 2016 02:33:38 -0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 24 Oct 2016 19:33:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.31,544,1473145200"; d="scan'208"; a="1049570052" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.60]) by orsmga001.jf.intel.com with ESMTP; 24 Oct 2016 19:33:36 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Tue, 25 Oct 2016 11:40:49 +0800 Message-Id: <1477366863-5246-2-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477366863-5246-1-git-send-email-yi.y.sun@linux.intel.com> References: <1477366863-5246-1-git-send-email-yi.y.sun@linux.intel.com> MIME-Version: 1.0 Cc: wei.liu2@citrix.com, he.chen@linux.intel.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, Yi Sun , jbeulich@suse.com, chao.p.peng@linux.intel.com Subject: [Xen-devel] [PATCH v3 01/15] docs: L2 Cache Allocation Technology (CAT) feature document. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Yi Sun --- docs/features/l2_cat.pandoc | 314 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 314 insertions(+) create mode 100644 docs/features/l2_cat.pandoc diff --git a/docs/features/l2_cat.pandoc b/docs/features/l2_cat.pandoc new file mode 100644 index 0000000..8544510 --- /dev/null +++ b/docs/features/l2_cat.pandoc @@ -0,0 +1,314 @@ +% Intel L2 Cache Allocation Technology (L2 CAT) Feature +% Revision 2.0 + +\clearpage + +# Basics + +---------------- ---------------------------------------------------- + Status: **Tech Preview** + +Architecture(s): Intel x86 + + Component(s): Hypervisor, toolstack + + Hardware: Atom codename Goldmont and beyond +---------------- ---------------------------------------------------- + +# Overview + +L2 CAT allows an OS or Hypervisor/VMM to control allocation of a +CPU's shared L2 cache based on application priority or Class of Service +(COS). Each CLOS is configured using capacity bitmasks (CBM) which +represent cache capacity and indicate the degree of overlap and +isolation between classes. Once L2 CAT is configured, the processor +allows access to portions of L2 cache according to the established +class of service (COS). + +# Technical information + +L2 CAT is a member of Intel PSR features and part of CAT, it shares +some base PSR infrastructure in Xen. + +## Hardware perspective + +L2 CAT defines a new range MSRs to assign different L2 cache access +patterns which are known as CBMs (Capacity BitMask), each CBM is +associated with a COS. + +``` + + +----------------------------+----------------+ + IA32_PQR_ASSOC | MSR (per socket) | Address | + +----+---+-------+ +----------------------------+----------------+ + | |COS| | | IA32_L2_QOS_MASK_0 | 0xD10 | + +----+---+-------+ +----------------------------+----------------+ + └-------------> | ... | ... | + +----------------------------+----------------+ + | IA32_L2_QOS_MASK_n | 0xD10+n (n<64) | + +----------------------------+----------------+ +``` + +When context switch happens, the COS of VCPU is written to per-thread +MSR `IA32_PQR_ASSOC`, and then hardware enforces L2 cache allocation +according to the corresponding CBM. + +## The relationship between L2 CAT and L3 CAT/CDP + +L2 CAT is independent of L3 CAT/CDP, which means L2 CAT would be enabled +while L3 CAT/CDP is disabled, or L2 CAT and L3 CAT/CDP are all enabled. + +L2 CAT uses a new range CBMs from 0xD10 ~ 0xD10+n (n<64), following by +the L3 CAT/CDP CBMs, and supports setting different L2 cache accessing +patterns from L3 cache. Like L3 CAT/CDP requirement, the bits of CBM of +L2 CAT must be continuous too. + +N.B. L2 CAT and L3 CAT/CDP share the same COS field in the same +associate register `IA32_PQR_ASSOC`, which means one COS associate to a +pair of L2 CBM and L3 CBM. +Besides, the max COS of L2 CAT may be different from L3 CAT/CDP (or +other PSR features in future). In some cases, a VM is permitted to have a +COS that is beyond one (or more) of PSR features but within the others. +For instance, let's assume the max COS of L2 CAT is 8 but the max COS of +L3 CAT is 16, when a VM is assigned 9 as COS, the L3 CBM associated to +COS 9 would be enforced, but for L2 CAT, the behavior is fully open (no +limit) since COS 9 is beyond the max COS (8) of L2 CAT. + +## Design Overview + +* Core COS/CBM association + + When enforcing L2 CAT, all cores of domains have the same default + COS (COS0) which associated to the fully open CBM (all ones bitmask) + to access all L2 cache. The default COS is used only in hypervisor + and is transparent to tool stack and user. + + System administrator can change PSR allocation policy at runtime by + tool stack. Since L2 CAT share COS with L3 CAT/CDP, a COS corresponds + to a 2-tuple, like [L2 CBM, L3 CBM] with only-CAT enabled, when CDP + is enabled, one COS corresponds to a 3-tuple, like [L2 CBM, + L3 Code_CBM, L3 Data_CBM]. If neither L3 CAT nor L3 CDP is enabled, + things would be easier, one COS corresponds to one L2 CBM. + +* VCPU schedule + + This part reuses L3 CAT COS infrastructure. + +* Multi-sockets + + Different sockets may have different L2 CAT capability (e.g. max COS) + although it is consistent on the same socket. So the capability of + per-socket L2 CAT is specified. + +## Implementation Description + +* Hypervisor interfaces: + + 1. Ext: Boot line parameter "psr=cat" now will enable L2 CAT and L3 + CAT if hardware supported. + + 2. New: SYSCTL: + - XEN_SYSCTL_PSR_CAT_get_l2_info: Get L2 CAT information. + + 3. New: DOMCTL: + - XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM: Get L2 CBM for a domain. + - XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM: Set L2 CBM for a domain. + +* xl interfaces: + + 1. Ext: psr-cat-show -l2 domain-id + Show L2 cbm for a domain. + => XEN_SYSCTL_PSR_CAT_get_l2_info / + XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM + + 2. Ext: psr-mba-set -l2 domain-id cbm + Set L2 cbm for a domain. + => XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM + + 3. Ext: psr-hwinfo + Show PSR HW information, including L2 CAT + => XEN_SYSCTL_PSR_CAT_get_l2_info + +* Key data structure: + + 1. Feature HW info + + ``` + struct psr_cat_hw_info { + unsigned int cbm_len; + unsigned int cos_max; + }; + ``` + + - Member `cbm_len` + + `cbm_len` is one of the hardware info of CAT. + + - Member `cos_max` + + `cos_max` is one of the hardware info of CAT. + + 2. Feature list node + + ``` + struct feat_node { + enum psr_feat_type feature; + struct feat_ops ops; + struct psr_cat_hw_info info; + uint64_t cos_reg_val[MAX_COS_REG_NUM]; + struct list_head list; + }; + ``` + + When a PSR enforcement feature is enabled, it will be added into a + feature list. The head of the list is created in psr initialization. + + - Member `feature` + + `feature` is an integer number, to indicate which feature the list entry + corresponds to. + + - Member `ops` + + `ops` maintains a callback function list of the feature. It will be introduced + in details later. + + - Member `info` + + `info` maintains the feature HW information which can be got through + psr_hwinfo command. + + - Member `cos_reg_val` + + `cos_reg_val` is an array to maintain the value set in all COS registers of + the feature. + + 3. Per-socket PSR features information structure + + ``` + struct psr_cat_socket_info { + unsigned int feat_mask; + unsigned int nr_feat; + struct list_head feat_list; + unsigned int cos_ref[MAX_COS_REG_NUM]; + spinlock_t ref_lock; + }; + ``` + + We collect all PSR allocation features information of a socket in + this `struct psr_cat_socket_info`. + + - Member `feat_mask` + + `feat_mask` is a bitmap, to indicate which feature is enabled on + current socket. We define `feat_mask` bitmap as: + + bit 0~1: L3 CAT status, [01] stands for L3 CAT only and [10] + stands for L3 CDP is enalbed. + + bit 2: L2 CAT status. + + - Member `cos_ref` + + `cos_ref` is an array which maintains the reference of one COS. + If the COS is used by one domain, the reference will increase one. + If a domain releases the COS, the reference will decrease one. The + array is indexed by COS. + + 4. Feature operation functions structure + + ``` + struct feat_ops { + void (*init_feature)(unsigned int eax, unsigned int ebx, + unsigned int ecx, unsigned int edx, + struct feat_node *feat, + struct psr_cat_socket_info *info); + int (*get_feat_info)(const struct feat_node *feat, enum cbm_type type, + uint32_t dat[], uint32_t array_len); + int (*get_val)(const struct feat_node *feat, unsigned int cos, + enum cbm_type type, uint64_t *val); + unsigned int (*get_max_cos_max)(const struct feat_node *feat); + unsigned int (*get_cos_num)(const struct feat_node *feat); + int (*get_old_val)(uint64_t val[], + const struct feat_node *feat, + unsigned int old_cos); + int (*set_new_val)(uint64_t val[], + const struct feat_node *feat, + unsigned int old_cos, + enum cbm_type type, + uint64_t m); + int (*compare_val)(const uint64_t val[], const struct feat_node *feat, + unsigned int cos, bool *found); + unsigned int (*get_cos_max_from_type)(const struct feat_node *feat, + enum cbm_type type); + unsigned int (*exceeds_cos_max)(const uint64_t val[], + const struct feat_node *feat, + unsigned int cos); + int (*write_msr)(unsigned int cos, const uint64_t val[], + struct feat_node *feat); + }; + ``` + + We abstract above callback functions to encapsulate the feature specific + behaviors into them. Then, it is easy to add a new feature. We just need: + 1) Implement such ops and callback functions for every feature. + 2) Register the ops into `struct feat_node`. + 3) Add the feature into feature list during CPU initialization. + +# User information + +* Feature Enabling: + + Add "psr=cat" to boot line parameter to enable all supported level CAT + features. + +* xl interfaces: + + 1. `psr-cat-show [OPTIONS] domain-id`: + + Show domain L2 or L3 CAT CBM. + + New option `-l` is added. + `-l2`: Specify cbm for L2 cache. + `-l3`: Specify cbm for L3 cache. + + If neither `-l2` nor `-l3` is given, level 3 is the default option. + + 2. `psr-cat-cbm-set [OPTIONS] domain-id cbm`: + + Set domain L2 or L3 CBM. + + New option `-l` is added. + `-l2`: Specify cbm for L2 cache. + `-l3`: Specify cbm for L3 cache. + + If neither `-l2` nor `-l3` is given, level 3 is the default option. + + 3. `psr-hwinfo [OPTIONS]`: + + Show L2 & L3 CAT HW informations on every socket. + +# References + +[Intel® 64 and IA-32 Architectures Software Developer Manuals, vol3, chapter 17.17](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html) + +# History + +------------------------------------------------------------------------ +Date Revision Version Notes +---------- -------- -------- ------------------------------------------- +2016-08-12 1.0 Xen 4.7 Initial design +2016-09-21 2.0 Xen 4.7 Changes according to review comments. + 1. L2 CBM bits should be continuous too. + 2. Describe 'struct feat_info' + 3. Update 'struct feat_list" description. + 4. Update 'struct feat_ops" description. + 5. Update `psr-cat-show` description. + 6. Update `psr-cat-cbm-set` description. + 7. Add volume and chapter info in References. +2016-10-24 3.0 Xen 4.7 Changes according to review comments. + 1. Update 'struct feat_list' to 'struct feat_node'. + 2. Update description of 'struct psr_cat_socket_info'. + 3. Update `psr-cat-show` description. + 4. Update `psr-cat-cbm-set` description. +---------- -------- -------- -------------------------------------------