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Fri, 11 Nov 2016 01:06:52 -0800 (PST) Received: from blr-ubuntu-linaro.wlan.qualcomm.com ([202.46.23.54]) by smtp.gmail.com with ESMTPSA id v82sm10193505pfi.6.2016.11.11.01.06.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Nov 2016 01:06:51 -0800 (PST) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Fri, 11 Nov 2016 14:36:46 +0530 Message-Id: <1478855206-19185-1-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: Julien Grall , Stefano Stabellini Subject: [Xen-devel] [PATCH] xen/arm: Add support for 16 bit VMIDs X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP VMID space is increased to 16-bits from 8-bits in ARMv8 8.1 revision. This allows more than 256 VMs to be supported by Xen. This change adds support for 16-bit VMIDs in Xen based on whether the architecture supports it. Signed-off-by: Bhupinder Thakur --- xen/arch/arm/p2m.c | 44 +++++++++++++++++++++++++++++++++++------ xen/include/asm-arm/p2m.h | 2 +- xen/include/asm-arm/processor.h | 17 +++++++++++++++- 3 files changed, 55 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index cc5634b..6ed7e5c 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -19,6 +19,7 @@ static unsigned int __read_mostly p2m_root_order; static unsigned int __read_mostly p2m_root_level; #define P2M_ROOT_ORDER p2m_root_order #define P2M_ROOT_LEVEL p2m_root_level +static unsigned int __read_mostly max_vmid; #else /* First level P2M is alway 2 consecutive pages */ #define P2M_ROOT_LEVEL 1 @@ -1219,7 +1220,7 @@ static int p2m_alloc_table(struct domain *d) p2m->root = page; - p2m->vttbr = page_to_maddr(p2m->root) | ((uint64_t)p2m->vmid & 0xff) << 48; + p2m->vttbr = page_to_maddr(p2m->root) | ((uint64_t)p2m->vmid << 48); /* * Make sure that all TLBs corresponding to the new VMID are flushed @@ -1230,20 +1231,47 @@ static int p2m_alloc_table(struct domain *d) return 0; } -#define MAX_VMID 256 +#ifdef CONFIG_ARM_64 +#define MAX_VMID (1UL << 16) +#else +#define MAX_VMID (1UL << 8) +#endif + #define INVALID_VMID 0 /* VMID 0 is reserved */ static spinlock_t vmid_alloc_lock = SPIN_LOCK_UNLOCKED; /* - * VTTBR_EL2 VMID field is 8 bits. Using a bitmap here limits us to - * 256 concurrent domains. + * VTTBR_EL2 VMID field is 8 or 16 bits. Aarch64 supports 16-bit VMID. + * Using a bitmap here limits us to 256 or 65536 (for Aarch64) concurrent + * domains. */ static DECLARE_BITMAP(vmid_mask, MAX_VMID); void p2m_vmid_allocator_init(void) { + unsigned int cpu; + set_bit(INVALID_VMID, vmid_mask); + + max_vmid = MAX_VMID; + +#ifdef CONFIG_ARM_64 + /* + * if any cpu does not support 16-bit VMID then restrict the + * max VMIDs which can be allocated to 256 + */ + for_each_online_cpu ( cpu ) + { + const struct cpuinfo_arm *info = &cpu_data[cpu]; + + if ( info->mm64.vmid_bits != VMID_16_BITS_SUPPORT ) + { + max_vmid = (1UL << 8); + break; + } + } +#endif } static int p2m_alloc_vmid(struct domain *d) @@ -1254,11 +1282,11 @@ static int p2m_alloc_vmid(struct domain *d) spin_lock(&vmid_alloc_lock); - nr = find_first_zero_bit(vmid_mask, MAX_VMID); + nr = find_first_zero_bit(vmid_mask, max_vmid); ASSERT(nr != INVALID_VMID); - if ( nr == MAX_VMID ) + if ( nr == max_vmid ) { rc = -EBUSY; printk(XENLOG_ERR "p2m.c: dom%d: VMID pool exhausted\n", d->domain_id); @@ -1646,6 +1674,10 @@ void __init setup_virt_paging(void) val |= VTCR_PS(pa_range); val |= VTCR_TG0_4K; + + /* set the VS bit only if 16 bit VMID is supported */ + if ( max_vmid == MAX_VMID ) + val |= VTCR_VS; val |= VTCR_SL0(pa_range_info[pa_range].sl0); val |= VTCR_T0SZ(pa_range_info[pa_range].t0sz); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index fdb6b47..bfcdbf1 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -30,7 +30,7 @@ struct p2m_domain { struct page_info *root; /* Current VMID in use */ - uint8_t vmid; + uint16_t vmid; /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 15bf890..4b6be3d 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -215,6 +215,7 @@ #define VTCR_PS(x) ((x)<<16) +#define VTCR_VS (_AC(0x1,UL)<<19) #endif #define VTCR_RES1 (_AC(1,UL)<<31) @@ -269,6 +270,11 @@ /* FSR long format */ #define FSRL_STATUS_DEBUG (_AC(0x22,UL)<<0) +#ifdef CONFIG_ARM_64 +#define VMID_8_BITS_SUPPORT 0x0 +#define VMID_16_BITS_SUPPORT 0x2 +#endif + #ifndef __ASSEMBLY__ struct cpuinfo_arm { @@ -337,7 +343,16 @@ struct cpuinfo_arm { unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; unsigned long __res0:32; - }; + + unsigned long hafdbs:4; + unsigned long vmid_bits:4; + unsigned long vh:4; + unsigned long hpds:4; + unsigned long lo:4; + unsigned long pan:4; + unsigned long __res1:8; + unsigned long __res2:32; + }; } mm64; struct {