From patchwork Wed Mar 29 05:11:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Gao X-Patchwork-Id: 9651461 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 77513602C8 for ; Wed, 29 Mar 2017 12:17:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66F8E27C0B for ; Wed, 29 Mar 2017 12:17:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B9DF28354; Wed, 29 Mar 2017 12:17:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.0 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIM_SIGNED, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DD32727C0B for ; Wed, 29 Mar 2017 12:17:06 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctCUw-00042I-Hm; Wed, 29 Mar 2017 12:14:46 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctCUu-000411-U5 for xen-devel@lists.xen.org; Wed, 29 Mar 2017 12:14:45 +0000 Received: from [193.109.254.147] by server-4.bemta-6.messagelabs.com id 82/E9-03012-435ABD85; Wed, 29 Mar 2017 12:14:44 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRWlGSWpSXmKPExsVywNwkQtd46e0 Ig0utxhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa0bLz2csBeeNK/om7GJrYGxR72Lk4mARuMUk sf7OXTYQR0hgGqPE9Mm9QA4nh4QAr8SRZTNYIWw/iRWrHzCB2EIC5RKL3k0Ds9kElCUufoWoF xGQlrj2+TIjyCBmgeNMEteuzmMESQgLeEm82TYHbBCLgKpEz/slYHFeAUeJx4+3M0MsUJCY8v A9mM0p4CRxftcZZohljhLrVjxkmcDIt4CRYRWjRnFqUVlqka6RhV5SUWZ6RkluYmaOrqGBmV5 uanFxYnpqTmJSsV5yfu4mRmCoMADBDsbzawMPMUpyMCmJ8p4wvB0hxJeUn1KZkVicEV9UmpNa fIhRhoNDSYJXZQlQTrAoNT21Ii0zBxi0MGkJDh4lEV6LxUBp3uKCxNzizHSI1ClGRSlx3t8gC QGQREZpHlwbLFIuMcpKCfMyAh0ixFOQWpSbWYIq/4pRnINRSZj3L8gUnsy8Erjpr4AWMwEtFr e5BbK4JBEhJdXAKCU0m39CltPkT3nPW5edd///btvWmQLv9QwDCzTLucuuqk15xO/d4/7hrZ/ jRG2xs+Wb53xQa9HzNLynkyXgt0PazjbtPef2uBf8QeZOD6XtZzx4t+LyvfD+f+vkUxP+huQ5 OZQZqN2c9eJuWtJj7y13u57+4D5RvKfC27Gj+SqbTwe/zcxiJZbijERDLeai4kQAuPeSdo8CA AA= X-Env-Sender: chao.gao@intel.com X-Msg-Ref: server-9.tower-27.messagelabs.com!1490789671!94414712!6 X-Originating-IP: [192.55.52.88] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjg4ID0+IDM3NDcyNQ==\n X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 21243 invoked from network); 29 Mar 2017 12:14:43 -0000 Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by server-9.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 29 Mar 2017 12:14:43 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490789683; x=1522325683; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=zAFlFl63FcRZlIlq981y994kFNt+pLJ5qwyb3aIzB1U=; b=PqiDq247NayaBbGuIvdHyrT2sipzm9ZozL1z+WxgIZbZ5YZ7jtrYKyTD WweZ2UErv+LcphPCFVq5UeERJg48OA==; Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2017 05:14:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,241,1486454400"; d="scan'208";a="80557054" Received: from skl-2s3.sh.intel.com ([10.239.48.35]) by orsmga005.jf.intel.com with ESMTP; 29 Mar 2017 05:14:41 -0700 From: Chao Gao To: xen-devel@lists.xen.org Date: Wed, 29 Mar 2017 13:11:54 +0800 Message-Id: <1490764315-7162-6-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1490764315-7162-1-git-send-email-chao.gao@intel.com> References: <1490764315-7162-1-git-send-email-chao.gao@intel.com> Cc: Kevin Tian , Jun Nakajima , George Dunlap , Andrew Cooper , Dario Faggioli , Jan Beulich , Chao Gao Subject: [Xen-devel] [PATCH v11 5/6] VT-d: introduce update_irte to update irte safely X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP We used structure assignment to update irte which was non-atomic when the whole IRTE was to be updated. It is unsafe when a interrupt happened during update. Furthermore, no bug or warning would be reported when this happened. This patch introduces two variants, atomic and non-atomic, to update irte. Both variants will update IRTE if possible. If the caller requests a atomic update but we can't meet it, we raise a bug. Signed-off-by: Chao Gao --- v11: - Add two variant function to update IRTE. Call the non-atomic one for init and clear operations. Call the atomic one for other cases. - Add a new field to indicate the remap_entry associated with msi_desc is initialized or not. v10: - rename copy_irte_to_irt to update_irte - remove copy_from_to_irt - change commmit message and add some comments to illustrate on which condition update_irte() is safe. xen/arch/x86/msi.c | 1 + xen/drivers/passthrough/vtd/intremap.c | 78 ++++++++++++++++++++++++++++++++-- xen/include/asm-x86/msi.h | 1 + 3 files changed, 76 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index 3374cd4..7ed1243 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -578,6 +578,7 @@ static struct msi_desc *alloc_msi_entry(unsigned int nr) entry[nr].dev = NULL; entry[nr].irq = -1; entry[nr].remap_index = -1; + entry[nr].remap_entry_initialized = false; entry[nr].pi_desc = NULL; } diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c index b992f23..b7f3cf1 100644 --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -169,10 +169,64 @@ bool_t __init iommu_supports_eim(void) return 1; } +static void update_irte(struct iremap_entry *entry, + const struct iremap_entry *new_ire, + bool atomic) +{ + if ( cpu_has_cx16 ) + { + __uint128_t ret; + struct iremap_entry old_ire; + + old_ire = *entry; + ret = cmpxchg16b(entry, &old_ire, new_ire); + + /* + * In the above, we use cmpxchg16 to atomically update the 128-bit + * IRTE, and the hardware cannot update the IRTE behind us, so + * the return value of cmpxchg16 should be the same as old_ire. + * This ASSERT validate it. + */ + ASSERT(ret == old_ire.val); + } + else + { + /* + * The following code will update irte atomically if possible. + * If the caller requests a atomic update but we can't meet it, + * a bug will be raised. + */ + if ( entry->lo == new_ire->lo ) + entry->hi = new_ire->hi; + else if ( entry->hi == new_ire->hi ) + entry->lo = new_ire->lo; + else if ( !atomic ) + { + entry->lo = new_ire->lo; + entry->hi = new_ire->hi; + } + else + BUG(); + } +} + +static inline void update_irte_non_atomic(struct iremap_entry *entry, + const struct iremap_entry *new_ire) +{ + update_irte(entry, new_ire, false); +} + +static inline void update_irte_atomic(struct iremap_entry *entry, + const struct iremap_entry *new_ire) +{ + update_irte(entry, new_ire, true); +} + + /* Mark specified intr remap entry as free */ static void free_remap_entry(struct iommu *iommu, int index) { - struct iremap_entry *iremap_entry = NULL, *iremap_entries; + struct iremap_entry *iremap_entry = NULL, *iremap_entries, new_ire = { }; struct ir_ctrl *ir_ctrl = iommu_ir_ctrl(iommu); if ( index < 0 || index > IREMAP_ENTRY_NR - 1 ) @@ -183,7 +237,7 @@ static void free_remap_entry(struct iommu *iommu, int index) GET_IREMAP_ENTRY(ir_ctrl->iremap_maddr, index, iremap_entries, iremap_entry); - memset(iremap_entry, 0, sizeof(*iremap_entry)); + update_irte_non_atomic(iremap_entry, &new_ire); iommu_flush_cache_entry(iremap_entry, sizeof(*iremap_entry)); iommu_flush_iec_index(iommu, 0, index); @@ -286,6 +340,7 @@ static int ioapic_rte_to_remap_entry(struct iommu *iommu, int index; unsigned long flags; struct ir_ctrl *ir_ctrl = iommu_ir_ctrl(iommu); + bool init = false; remap_rte = (struct IO_APIC_route_remap_entry *) old_rte; spin_lock_irqsave(&ir_ctrl->iremap_lock, flags); @@ -296,6 +351,7 @@ static int ioapic_rte_to_remap_entry(struct iommu *iommu, index = alloc_remap_entry(iommu, 1); if ( index < IREMAP_ENTRY_NR ) apic_pin_2_ir_idx[apic][ioapic_pin] = index; + init = true; } if ( index > IREMAP_ENTRY_NR - 1 ) @@ -353,7 +409,11 @@ static int ioapic_rte_to_remap_entry(struct iommu *iommu, remap_rte->format = 1; /* indicate remap format */ } - *iremap_entry = new_ire; + if ( init ) + update_irte_non_atomic(iremap_entry, &new_ire); + else + update_irte_atomic(iremap_entry, &new_ire); + iommu_flush_cache_entry(iremap_entry, sizeof(*iremap_entry)); iommu_flush_iec_index(iommu, 0, index); @@ -567,7 +627,10 @@ static int msi_msg_to_remap_entry( { /* Free specified unused IRTEs */ for ( i = 0; i < nr; ++i ) + { free_remap_entry(iommu, msi_desc->remap_index + i); + msi_desc[i].remap_entry_initialized = false; + } spin_unlock_irqrestore(&ir_ctrl->iremap_lock, flags); return 0; } @@ -639,7 +702,14 @@ static int msi_msg_to_remap_entry( remap_rte->address_hi = 0; remap_rte->data = index - i; - *iremap_entry = new_ire; + if ( msi_desc->remap_entry_initialized ) + update_irte_atomic(iremap_entry, &new_ire); + else + { + update_irte_non_atomic(iremap_entry, &new_ire); + msi_desc->remap_entry_initialized = true; + } + iommu_flush_cache_entry(iremap_entry, sizeof(*iremap_entry)); iommu_flush_iec_index(iommu, 0, index); diff --git a/xen/include/asm-x86/msi.h b/xen/include/asm-x86/msi.h index fc9ab04..a0bd3af 100644 --- a/xen/include/asm-x86/msi.h +++ b/xen/include/asm-x86/msi.h @@ -118,6 +118,7 @@ struct msi_desc { struct msi_msg msg; /* Last set MSI message */ int remap_index; /* index in interrupt remapping table */ + bool remap_entry_initialized; const struct pi_desc *pi_desc; /* pointer to posted descriptor */ uint8_t gvec; /* guest vector. valid when pi_desc isn't NULL */ };