From patchwork Thu Mar 30 09:02:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Chen X-Patchwork-Id: 9653315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3ED92602C8 for ; Thu, 30 Mar 2017 09:06:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 280A926E4F for ; Thu, 30 Mar 2017 09:06:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1CA5728578; Thu, 30 Mar 2017 09:06:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6E80026E4F for ; Thu, 30 Mar 2017 09:06:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctVz2-0004bH-Bw; Thu, 30 Mar 2017 09:03:08 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ctVz0-0004bB-QT for xen-devel@lists.xen.org; Thu, 30 Mar 2017 09:03:07 +0000 Received: from [85.158.143.35] by server-7.bemta-6.messagelabs.com id 6A/6A-04817-AC9CCD85; Thu, 30 Mar 2017 09:03:06 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA1VSa0gUYRT1m5ndHcWVcVfxKu6CW4FUyookpgV KhVJoGSSiQc7m5C7tQ3bWWumPouULUUHxgamlP0zLH/ZQMStNSSXTJEXzUZKvTDIVKjS1mR01 +37d851zzz0XLonLMsUeJGO1MGYjrVeJHQjv6/hpn97eiRh1bpMosHalhghB4d1tG9gFFCvSG TUma7xIu/LgtjgpLdxaWheXiuaCcpADSVCpOGR9/4PxQEYVY/B2cYMD9hx4g8H7dBeeQNQQgq cdtUhQvUCQNt+DC6AQg/W1WbEAqhBsLk8QfL+Y8oK8wjRb7UIpoCGnQsKLcKoSQdFWnYgn5NQ Z+PF6DfE1QR2CwYw5W4OUCoHh8XzbP1BKGHuXjQv/ztBbNmPT4BRAx8ICLoRVQMlE/47eHUbG BrlhJFcfgL6MSH4uUOMEpLdv4wJ4IoKf66UioSECOnOF5YBP15jdugMGCPjU3i0SwEMxZBY12 GY4UTJo/vwcE4gWDPLuTEkErySomfm1E8QI5V8nJYJoDYPZ+pId0RcJdA1bhdoTNqraiAJ0pH zfguX7FqxGWD3yZhnzDcbs46/21Zh1iVqLgdbpffzUAb4GhmXpREZPa1jfqyZDE+LOwY57LWj zUVQncicxlav08d2JGJmTxpSQoqVZ7RVzsp5hO5EnSapAOtrDcc5mJpGxXtPpuZvapYF0VLlI FdxVyaRsEm1gdYkC1Yf8yftbbUsYubX6agmTEUaTkfFwk1byThQv1SYb94x273MIKTzkUsRFk zkmMWaDzvI/v4jcSKSSS6d4F0ed0bI3b5GLgnFR3E585KNY6H+URyqSK26ZElwz486JvPKPpS pnJy2RppthXdMmt0DT6kHnuukSg744+lvdQCiyz9dEROm3w5TxgQON532CjSGDzZmhKY4f7PC Lp9JHW1dCrUfLVpT5wb+ro8+GWQvSlEHzEff6l9VRI5cKKp5dlsjLnFtbA8pe+sbaq08elwTk ZsGAimC1tN9h3MzSfwFuHFSvmgMAAA== X-Env-Sender: Wei.Chen@arm.com X-Msg-Ref: server-4.tower-21.messagelabs.com!1490864584!54964455!1 X-Originating-IP: [40.107.3.68] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 34615 invoked from network); 30 Mar 2017 09:03:05 -0000 Received: from mail-eopbgr30068.outbound.protection.outlook.com (HELO EUR03-AM5-obe.outbound.protection.outlook.com) (40.107.3.68) by server-4.tower-21.messagelabs.com with AES256-SHA256 encrypted SMTP; 30 Mar 2017 09:03:05 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=8Zu8y8mhax/EKxYdhZpmDuxLS2vC4iw4LXzURYI/z3Y=; b=ovJGzk5SDBNK6qXIVS269n5ZaBFflq+1V3uGFzuS/W8bKJ6bAzt5w27je7wU4CNv8cAswi114XD3KujEL/XqMg/4PoHt7P5CGNULfi28MGihLjiNRYqPRGh3C87KenBwDHp9p1jZaLba406KH9F5nVt3vALA8qAoJJczvh+eHXI= Received: from VI1PR08CA0056.eurprd08.prod.outlook.com (10.166.137.24) by VI1PR0801MB1678.eurprd08.prod.outlook.com (10.168.66.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.991.14; Thu, 30 Mar 2017 09:02:54 +0000 Received: from AM5EUR03FT026.eop-EUR03.prod.protection.outlook.com (2a01:111:f400:7e08::204) by VI1PR08CA0056.outlook.office365.com (2a01:111:e400:c53b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1005.10 via Frontend Transport; Thu, 30 Mar 2017 09:02:53 +0000 Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 217.140.96.140 as permitted sender) receiver=protection.outlook.com; client-ip=217.140.96.140; helo=nebula.arm.com; Received: from nebula.arm.com (217.140.96.140) by AM5EUR03FT026.mail.protection.outlook.com (10.152.16.155) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.1.1005.5 via Frontend Transport; Thu, 30 Mar 2017 09:02:53 +0000 Received: from P300.p300.shanghai.arm.com (10.1.2.79) by mail.arm.com (10.1.106.66) with Microsoft SMTP Server id 14.3.294.0; Thu, 30 Mar 2017 10:02:36 +0100 From: Wei Chen To: Date: Thu, 30 Mar 2017 17:02:33 +0800 Message-ID: <1490864553-17245-1-git-send-email-Wei.Chen@arm.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:217.140.96.140; IPV:CAL; SCL:-1; CTRY:GB; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(39400400002)(39850400002)(39410400002)(39840400002)(39450400003)(39860400002)(2980300002)(438002)(199003)(189002)(104016004)(50226002)(77096006)(38730400002)(5660300001)(110136004)(48376002)(8676002)(8936002)(189998001)(54906002)(6306002)(4326008)(6666003)(5003940100001)(106466001)(6916009)(2351001)(2906002)(47776003)(86362001)(575784001)(50986999)(36756003)(356003)(305945005)(50466002); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0801MB1678; H:nebula.arm.com; FPR:; SPF:Pass; MLV:sfv; A:1; MX:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; AM5EUR03FT026; 1:O8qoYPnPkqxkolHVTdxVGI+7RKCaTyfOiy+3ZszWZohC0PavzkdlnogeuT2nTWtAYNJOZbzAs00w4nIwokOnYTZIc2rKRxa3nQ0Tq9+21xek5HKhYwOslcQ3cMUci5E3kR2Z0Eogq+Js17cYcKRDxvt/xFVEnEDVNdEtwUyvSIsupxWtYS0ZphKsOjmFKJi1fn2a2YWmZqTVt+hc94bsaCJpmegKMMhTP4St8m3iaO/PdGm1FeNuCMbqPEfPdOIpriPEeuZKspEUQB98TeViJbc4qgT4jit+V140G7YA0pWH+3aMAOlXEU6Uc7AwLldXKh+2tYEDpWfE1yN+v/jIR7ROaVJORgr9jm7VDcJa7CdM5HF3IcCGy3gFqhjEOw3EMSt2vbVrKs6uP1EEkQCpy1ZabEmDsURwrogR8wBqGc1v4Vvp+pXFJfVN1phpWUBRFuYg+FFDBOLS419fUX/1plboqpGLlRBtfKvuBxTBRuMMLxieC+R0rVvchbk7maV+VoqXX6Pn4q7rN3EN5lYvhWveEF6Km73GckqoioFIZ4cv6q7yBUEwStInD7UzHp8TOP/AacK2U6jqcOrLD3jQqxhzt15Cp92+PuuWTgYY0KuUhH3ypn3MEYUm8+rRcfe/ X-MS-Office365-Filtering-Correlation-Id: 00d343ee-d50f-4702-b7d5-08d4774b8d0e X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(8251501002)(2017030254075)(201703131423075)(201703031133081)(201702281549075); SRVR:VI1PR0801MB1678; X-Microsoft-Exchange-Diagnostics: 1; VI1PR0801MB1678; 3:ckuvJu/MhDiZWLM4ZOtcXUC/+y/wgY08SBW0KsQH5Gi70mCA5O32yfZMlJKm+6j+fFpMMhvOsYp/nM4OYVy2P2qyH1lCu2w6fT5W/CYT1H3MtkPaaMWbxK01VkAMbjFKfknSjuQyMDtqfRPuy3m24DZpVBeUt1O7mEsWqcRmyyFN3VDVeRflfSvkpq6sJdyxT6gSSna7XhLUY0oSsmCfU0FiM9iYxdYubiC3/FEXFMRPNO8mYgtxJRrjBxvIjUM9U8TCSoux4rWl4wkMIt//sQjFVAG26PjxFPakqF24nBcVQ0JEWf2xTgJOjQ2gyfnXjwaqMu9xrl2/z8h94Jm/sZyf0P8optMrSWpABG3EvOY5s+De1eBZo5hMHoyUZtL/hOMMg9KmLOj75eq3ImrnH9BBL9ZQ+c6wcpkF6M7iKK9tlAUapRriF4Z8yTvvsbSxBZ681H4TD/DF2HY0TWBNzyKzQVKuRNlUe1DE7otsXgp4P2agVlitx1+SwDkaeh8w9OGNXo7zZWJFjYtJJdnm6w== X-Microsoft-Exchange-Diagnostics: 1; VI1PR0801MB1678; 25:F37WDXw30uMEE1JtljirZZoHhnIINvyM3M9esf8CWW97rJdygRh6BeNL4n+HB0W05tcO1UQ2lvA44Ikfa27WY+v9BofiOdzTtex4POz2HmnjZeZelgzGX1bDGe5cq2GatCFvVxhZ0ci0FEnEsMZPm5bAkCzme4f55eDGx3AVLv6xw7sWPcqBwqC1OqzyKB7PZUjnbzrdG8xk6OccdSqSIR4MCeVuBva+RIEbp4YKV25hyVvYiiW100p9rDITO6RycanaeF8Gb2XbrspaBh6h5rXL1XtImiY6SUdPOBJKwm1vmKCTHA8v83OZoGCSLD1yen8Mkl0S8Up/of2C0jn1H4EZMr8+KtBzkGw7/RmRIrZE99nXQOEBn5EsvDZqUIlVF6wN4mWXsRfnyMIs7SJvyxzfAtxdMgBc2+yyYvgz+8pdgXikTlRKYUCHHT3+odyz/hVN3dqS+aHiMjOE+aewmA==; 31:VF9FdDXCn1pQxyx4BRMEWxXfv+z4xWc9g7wtoQ38RV0ky9zrvk72LnWTuoAETjiU+FjfHmBz/D8C3D6nahlwMv8hLgN8cQ/H/azCTC8bmVokwYZW+8djL6ok5DYnXPK3VoPyp/VWOWJXvdTthtgkPvkO85za+0fgeXNa60RfP+5qqmZF1HMSzsXEabNJU7MgkoZPA1hKuMEitLe3wmPHOmbyfp9j4U9K/q9AxRG6oojDtzD/RuYXwVdKdw2UxhXS7G0DCbQ1AqT5M4+TJZ5S9g== NoDisclaimer: True X-Microsoft-Exchange-Diagnostics: 1; VI1PR0801MB1678; 20:xs0ZXGOSDqzN2iFvIJRDoY4gyC/35reZnTqb53rZX5eOf37ei4RtbyVub2Rg82mltJ8HxaS2Bj/tHaIOYsT7PYZxaKQhwgE5bioDmC5bKVZxzN/ppVYJlMiv78gTDNbJmDWUIh5JmJTvJUAdsBM2mIzzY2oWYyYYO9DtbRi6jke5/KbOXCzp2MpdRn/5hyCdpyTZS1qrMLmWcL2F26m0VeBB7ney5jUDj3L/mLdNeOMFfIvNbo4T61HEac11rQ/M X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(250305191791016)(180628864354917)(22074186197030)(146099531331640); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040450)(601004)(2401047)(13013025)(8121501046)(5005006)(13020025)(13023025)(13024025)(3002001)(10201501046)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(20161123560025)(20161123562025)(20161123564025)(20161123555025)(6072148); SRVR:VI1PR0801MB1678; BCL:0; PCL:0; RULEID:; SRVR:VI1PR0801MB1678; X-Microsoft-Exchange-Diagnostics: 1; VI1PR0801MB1678; 4:kKShHrIhWbeGkCEiIwYEIk74o9B0IX5H86S1zmexuQnZH6+B0Ff/cYbETuZdnMTWsAGOynIBvMPr4aUswWF+vR8QE5gYAo0afEf/wBT6m8MbkmLWWdFtdVxw+VbOMjc/NzusGOMULZmxNm4VKnXJh4skuYANu/sEDpdELwLK8O2s+C1qCKh02zvd3+8aIc2v6X7ogc4IlXboCJjD0Kcee9DIZmL9SpJ7KUbfAesglroye37EzAPGksqTWDEOY2byflsGzIYn68oV5RFoT6nDgzCrS2hvwuFsa+QJG35kDfHkAgPAsw+ou4xBHYUW3NRbDuLPcSyF1w/E4t5P2GH8fE1xlGZlWZ2Q7rTzaei+Lpx/bVCYoZqmvaThHiGEL8ujWI6CVyaXx29b4LBZbcxzNrdwrnM5uQ/K5r5Oz8JZYsKdE/SguH0Zl2ONUJvUnGgBbvI7LIpSSyAdTs2PckdIWs9MbpJ138gqMfM84omhJ9UkpODrfYWwBJspVz5FvgVdgnIAP4DrxUnvm9n6UbIU0lrlwqlQEwTlBY42SzoAeyD0JH+/WfTiE5CA8ci5LUpG7hZXdJjHloRCWgZSSF/gGzvS7fFCYD0jTGTd557byQQF1pvbJmRb7IXQesdX22Y8z1S7CVa5n70DVjiLaqhZEwReZAOE1e2odqMAuArO5cWbS6zDKMPE7kVJMWFSFj/lzJNn1QrvjrjTC9s9GAOmccNdSxrG4yDTtCRPooueZkpuBgnvaSDXJShxHEHmQm0GP6kp/VNtI0WxG1Mgx+m0Ecik6vDKO3ObIj2+BMG6BaWTjEgxdqkr+P1Zlg/XrErpn6i0MHPgdE/W0x9mbW36C5z6L+K3aiQiFksrtXvZi3xL9w+NIRg5WD5EQI8mUjzKNwF0OddNjNieTzMOfpDyqoYDjHZ/Xlx16ShB0+jL9Tc= X-Forefront-PRVS: 02622CEF0A X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; VI1PR0801MB1678; 23:SA11Jq3hYuz+B50L0JXEJks/YJmeWxWonVotWCO?= =?us-ascii?Q?aDunULY0+HDZJmN3nuua+xSTKnAwRnTAW6D5A/TxPbNjWcsWPxQbO7lNvfl6?= =?us-ascii?Q?yTdjAwQ3kbOFLvSlBQOmFO8xJVXIX8NejG31gMOmGHkPXtTwXsshmwp8hGo5?= =?us-ascii?Q?niRHv92Jf1eyLlBKVLlntSBA7vhdAK7yfL+LvqrT5nXaoXsgPPnGA+vi+Dnm?= =?us-ascii?Q?aqqBLOF3XZHAon5tWOp+6KJIUHkITAs5c0WrEO4VV4HohJed5gN2lhwavmK+?= =?us-ascii?Q?l7d3oFk3QYqo8H+wFE9Re5kWCEhmd/0MJz4PpplMWGUs5HHBrO3H9No4N4hK?= =?us-ascii?Q?IPVe1tLH30cwVCgv/2ALSRRDy17hTVgHa50jezIHaG0QhXTgdtO/bd8XC/z4?= =?us-ascii?Q?l+SS1AUAlaflsLxvj6thuXx+gDO9S0jRhLrYccmZilDvyiyZqi+oGCQux2hB?= =?us-ascii?Q?/Cp2yYgkR922ae9ceFDwzmhRBs6XIjnypkmvy+JdbkKYjmlRO86vAPz0vVYL?= =?us-ascii?Q?5qHA1I52qUBet8A9a+6EnQpAL7JbUyhz5GVir9Z8KgcMnCrw/i9PcEVLGhPu?= =?us-ascii?Q?+tABcRI1/g4uSHQWsxx1HkjRBymG8VJ7PKDDpzWyawr0xdmMeTMrOZsr9/Jb?= =?us-ascii?Q?N/Kbm6Sx1so7V9eFBO2d3gGE898vrQJcTxZKtSUp+/8pHXIQPJO4CkKDak7e?= =?us-ascii?Q?LNwPu8NtPTwDjN6sqmmrmrjrtJ+a3gmoUnz4UWzmPn7jARkfxAIOjN4Lo6W7?= =?us-ascii?Q?Z0wkRPEZntdoAv9dHSRap0pRqn7mFppU2ZD3/mMuq4iXeBd3R6YmpGZwOM9l?= =?us-ascii?Q?gB+DPm63IXUa6vadNSymWeLGTWPPVD0y+Eb4z1FvmJEoyn0LVe2QfkJLeFUS?= =?us-ascii?Q?fWNE91RObxho0v5GpH8d4GrSwNg7Et4lIz8b2PucWJXxGEKzN4TvkK3As46J?= =?us-ascii?Q?N/oqkXeB7ytj214bFbeb+lsc8y2Co8/eOmjc58M8vNA=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1; VI1PR0801MB1678; 6:iBnl8gv9/Rru7IAMM6mmDxN2tWAcmCSeJPThN546R/Pt22fPPKcBYujL57X4XH6DBf59DaprYivwEjzfctn0ZiZEBD4hLl7Ra0xhVrBJB5bv4j5LVh3u7xcivAunCLY4ima1iD7Qg4+Ia6fV6PvUMQWZ04qu2bnUUrhrzc3hBelEo0O1AipoQIen1qh1XrbpokXFZAtFcZIhHxXRIEA6q+OfijcuJn68oD5gM8exX2G8XAzREH8FNtGHZvonuynEMl657/mXFgTnvkk2ODPA232kkVXAQv/5wwKVQHX1K4BnESXS2W5rHFBMEkP4xovLdcUAVO7hgvh/FpnX1jf0pAvQyyGjNtyPmKCwVsO+JfpkoqFRrZlHgYAz4uCJh8Tc/PGWCS+F4t36jSje15MncksWV6/G0leY0DiRLWr/tEA=; 5:XX3B9SmllqQr7IbpyiGROlLz3FiyqFeHvqFSUJflwS9AGULyHMpJWNUGnZOPJYshL32iobDUURU4XS2mX8ldtkup1R6TTB028gWypumArStdLN53ZGX/yJab2P207mC1E8GO89bmi69PvYX4aOJ6bQ==; 24:owAOZOcAPVgyoaNIc8c4lH3IZUQEa0UT9tezjFd/abxGesJ5bV5k9AB8hsTa9/C5Ccmmd9c0lYoC9qnrQfOnTV5Kfg3ZgWOslajMviS5DVA= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; VI1PR0801MB1678; 7:UO/37tP1wPEFWTHHGIj9ZqbRg3uKMKx3kQBTQll7CWeMy6f3XdCxcWCI+i/lkxBF9/TRfVNSIrhCbt9v7W6Ih1TNVpCtaPNPwil1MWWKtnwfiizZ5zaHDYQ5rnHPlObQeA5lR/5hPit764coi7OcklVwuhXYmXkSPpL5o9lbkFWxtc3XoT4gnzfMsMbAVEP/SK3AgLaU60vmGJfd84Lt3Bl5B7OIe2jvRBHSKhWGe0pmM5pwNnHzvX7YT3iX3oReuHlFACBDdQYwMPI2XgPi4bz0rSmEtEH0k4scYjbjTBIiagmKF687GrHSdJR/GkbJD994tnRZFxbJleapv5/+RA== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2017 09:02:53.6230 (UTC) X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[217.140.96.140]; Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0801MB1678 Cc: sstabellini@kernel.org, wei.chen@arm.com, steve.capper@arm.com, Kaly.Xin@arm.com, julien.grall@arm.com, nd@arm.com Subject: [Xen-devel] [PATCH v3] xen/arm32: Introduce alternative runtime patching X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch is based on the implementation of ARM64, it introduces alternative runtime patching to ARM32. This allows to patch assembly instruction at runtime to either fix hardware bugs or optimize for certain hardware features on ARM32 platform. Xen hypervisor is using ARM execution state only on ARM32 platform, Thumb is not used. So, the Thumb only branch instructions (CBZ, CBNZ, TBB and TBH) are not considered in alternatives. The left ARM32 branch instructions are BX, BLX, BL and B. The instruction BX is taking a register in parameter, so we don't need to rewrite it. The instructions BLX, BL and B are using the similar encoding for the offset and will avoid specific case when extracting and updating the offset. In this patch, we include alternative.h header file to livepatch.c directly for ARM32 compilation issues. When the alternative patching config is enabled, the livepatch.c will use the alternative functions. In this case, we should include the alternative header file to this file. But for ARM64, it does not include this header file directly. It includes this header file indirectly through: sched.h->domain.h->page.h->alternative.h. But, unfortunately, the page.h of ARM32 doesn't include alternative.h, and we don't have the reason to include it to ARM32 page.h now. So we have to include the alternative.h directly in livepatch.c. Signed-off-by: Wei Chen Reviewed-by: Konrad Rzeszutek Wilk --- v2->v3: 1. Introduce a macro to cache blx. 2. Check the instruction conditional bits in open-code to avoid recognizing blx in the macros of b and bl. 3. Explain in code comment, why we mask the H bit for blx in macro. --- xen/arch/arm/Kconfig | 2 +- xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/insn.c | 91 ++++++++++++++++++++++++++++++++++++++++ xen/common/livepatch.c | 1 + xen/include/asm-arm/arm32/insn.h | 75 +++++++++++++++++++++++++++++++++ xen/include/asm-arm/insn.h | 2 + 6 files changed, 171 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/arm32/insn.c create mode 100644 xen/include/asm-arm/arm32/insn.h diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2e023d1..43123e6 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -12,11 +12,11 @@ config ARM_32 config ARM_64 def_bool y depends on 64BIT - select HAS_ALTERNATIVE select HAS_GICV3 config ARM def_bool y + select HAS_ALTERNATIVE select HAS_ARM_HDLCD select HAS_DEVICE_TREE select HAS_MEM_ACCESS diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 4395693..0ac254f 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -4,6 +4,7 @@ obj-$(EARLY_PRINTK) += debug.o obj-y += domctl.o obj-y += domain.o obj-y += entry.o +obj-y += insn.o obj-$(CONFIG_LIVEPATCH) += livepatch.o obj-y += proc-v7.o proc-caxx.o obj-y += smpboot.o diff --git a/xen/arch/arm/arm32/insn.c b/xen/arch/arm/arm32/insn.c new file mode 100644 index 0000000..7a5dbc5 --- /dev/null +++ b/xen/arch/arm/arm32/insn.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2017 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include +#include +#include +#include + +/* Mask of branch instructions' immediate. */ +#define BRANCH_INSN_IMM_MASK GENMASK(23, 0) +/* Shift of branch instructions' immediate. */ +#define BRANCH_INSN_IMM_SHIFT 0 + +static uint32_t branch_insn_encode_immediate(uint32_t insn, int32_t offset) +{ + uint32_t imm; + + /* + * Encode the offset to imm. All ARM32 instructions must be word aligned. + * Therefore the offset value's bits [1:0] equal to zero. + * (see ARM DDI 0406C.c A8.8.18/A8.8.25 for more encode/decode details + * about ARM32 branch instructions) + */ + imm = ((offset >> 2) & BRANCH_INSN_IMM_MASK) << BRANCH_INSN_IMM_SHIFT; + + /* Update the immediate field. */ + insn &= ~(BRANCH_INSN_IMM_MASK << BRANCH_INSN_IMM_SHIFT); + insn |= imm; + + return insn; +} + +/* + * Decode the branch offset from a branch instruction's imm field. + * The branch offset is a signed value, so it can be used to compute + * a new branch target. + */ +int32_t aarch32_get_branch_offset(uint32_t insn) +{ + uint32_t imm; + + /* Retrieve imm from branch instruction. */ + imm = ( insn >> BRANCH_INSN_IMM_SHIFT ) & BRANCH_INSN_IMM_MASK; + + /* + * Check the imm signed bit. If the imm is a negative value, we + * have to extend the imm to a full 32 bit negative value. + */ + if ( imm & BIT(23) ) + imm |= GENMASK(31, 24); + + return (int32_t)(imm << 2); +} + +/* + * Encode the displacement of a branch in the imm field and return the + * updated instruction. + */ +uint32_t aarch32_set_branch_offset(uint32_t insn, int32_t offset) +{ + /* B/BL support [-32M, 32M) offset (see ARM DDI 0406C.c A4.3). */ + if ( offset < -SZ_32M || offset >= SZ_32M ) + { + printk(XENLOG_ERR + "%s: new branch offset out of range.\n", __func__); + return BUG_OPCODE; + } + + return branch_insn_encode_immediate(insn, offset); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/common/livepatch.c b/xen/common/livepatch.c index 246e673..f14bcbc 100644 --- a/xen/common/livepatch.c +++ b/xen/common/livepatch.c @@ -25,6 +25,7 @@ #include #include +#include #include /* diff --git a/xen/include/asm-arm/arm32/insn.h b/xen/include/asm-arm/arm32/insn.h new file mode 100644 index 0000000..b5c60c2 --- /dev/null +++ b/xen/include/asm-arm/arm32/insn.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2017 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __ARCH_ARM_ARM32_INSN +#define __ARCH_ARM_ARM32_INSN + +#include + +#define __CONDITIONAL_INSN(insn) (((insn) >> 28) != 0xf) + +#define __AARCH32_INSN_FUNCS(abbr, mask, val) \ +static always_inline bool_t aarch32_insn_is_##abbr(uint32_t code) \ +{ \ + return (code & (mask)) == (val); \ +} + +/* Conditional branch instructions */ +__AARCH32_INSN_FUNCS(b, 0x0F000000, 0x0A000000) +__AARCH32_INSN_FUNCS(bl, 0x0F000000, 0x0B000000) + +/* Unconditional branch instructions */ +/* + * From ARM DDI 0406C.c Section A8.8.25. We can see blx has a H bit. + * In an ARM/Thumb instructions mixed running environment, this bit + * can be 1 or 0. Although Xen is only using the ARM instructions + * and the H bit is always 0. We mask this bit to catch both of these + * two encodings for future-proof. + */ +__AARCH32_INSN_FUNCS(blx, 0x0E000000, 0x0A000000) + +int32_t aarch32_get_branch_offset(uint32_t insn); +uint32_t aarch32_set_branch_offset(uint32_t insn, int32_t offset); + +/* Wrapper for common code */ +static inline bool insn_is_branch_imm(uint32_t insn) +{ + /* Check conditional branch instructions */ + if ( __CONDITIONAL_INSN(insn) ) + return ( aarch32_insn_is_b(insn) || aarch32_insn_is_bl(insn) ); + + /* Check unconditional branch instructions */ + return aarch32_insn_is_blx(insn); +} + +static inline int32_t insn_get_branch_offset(uint32_t insn) +{ + return aarch32_get_branch_offset(insn); +} + +static inline uint32_t insn_set_branch_offset(uint32_t insn, int32_t offset) +{ + return aarch32_set_branch_offset(insn, offset); +} + +#endif /* !__ARCH_ARM_ARM32_INSN */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/insn.h b/xen/include/asm-arm/insn.h index a205ceb..3489179 100644 --- a/xen/include/asm-arm/insn.h +++ b/xen/include/asm-arm/insn.h @@ -5,6 +5,8 @@ #if defined(CONFIG_ARM_64) # include +#elif defined(CONFIG_ARM_32) +# include #else # error "unknown ARM variant" #endif