From patchwork Wed Apr 5 23:19:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9665883 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8735760364 for ; Wed, 5 Apr 2017 23:22:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7948E2816B for ; Wed, 5 Apr 2017 23:22:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6DFAE2857E; Wed, 5 Apr 2017 23:22:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0D4B128584 for ; Wed, 5 Apr 2017 23:22:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cvuEq-0005IE-Dv; Wed, 05 Apr 2017 23:21:20 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cvuEp-0005F1-AD for xen-devel@lists.xenproject.org; Wed, 05 Apr 2017 23:21:19 +0000 Received: from [85.158.143.35] by server-3.bemta-6.messagelabs.com id DB/4D-27751-EEB75E85; Wed, 05 Apr 2017 23:21:18 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCLMWRWlGSWpSXmKPExsVysyfVTfdt9dM Ig/uXbSy+b5nM5MDocfjDFZYAxijWzLyk/IoE1oyln8oL5ihWPH71kr2BcYZkFyMXh5DAJkaJ H8cmsUA4exklmh7dYe1i5ORgE9CV2HHzNTOILSIQKjHn5yMgm4ODWaBSonsRP0hYWMBcYveeB WwgNouAqsTptSfBynkF3CUevmhgAymXEJCTuPIvASTMCRR+2XqMBcQWEnCTuDZxKssERu4FjA yrGDWKU4vKUot0jUz1kooy0zNKchMzc3QNDcz0clOLixPTU3MSk4r1kvNzNzECfcsABDsYVy0 IPMQoycGkJMqr4PMkQogvKT+lMiOxOCO+qDQntfgQowwHh5IE77aqpxFCgkWp6akVaZk5wCCD SUtw8CiJ8L4HSfMWFyTmFmemQ6ROMSpKifNuAkkIgCQySvPg2mCBfYlRVkqYlxHoECGegtSi3 MwSVPlXjOIcjErCvDdBpvBk5pXATX8FtJgJaPGTOw9BFpckIqSkGhh9Eo99O/st8fGP4k0HT1 rq2Uy592/Gvn4JB6sp6vdP3xG8/GLL6ptb5xRZ7tmqvG3auZqkoOjpXmy+W06xf/7jPat5nyO XOoujT6jqkhYXsbiWg0mCx3gmP2/JF8n5vLfNuq0xtaHH4T+LYlTyxML5cXzhF1Y+Eff8qfLB J1Zr7Z0jPE1tGkZKLMUZiYZazEXFiQBaGDVRZwIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-12.tower-21.messagelabs.com!1491434477!62419708!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 16220 invoked from network); 5 Apr 2017 23:21:17 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-21.messagelabs.com with SMTP; 5 Apr 2017 23:21:17 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 268C2344; Wed, 5 Apr 2017 16:21:17 -0700 (PDT) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D96223F4FF; Wed, 5 Apr 2017 16:21:15 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 6 Apr 2017 00:19:18 +0100 Message-Id: <1491434362-30310-27-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1491434362-30310-1-git-send-email-andre.przywara@arm.com> References: <1491434362-30310-1-git-send-email-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Shanker Donthineni , Vijay Kilari Subject: [Xen-devel] [PATCH v5 26/30] ARM: vITS: handle INV command X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The INV command instructs the ITS to update the configuration data for a given LPI by re-reading its entry from the property table. We don't need to care so much about the priority value, but enabling or disabling an LPI has some effect: We remove or push virtual LPIs to their VCPUs, also check the virtual pending bit if an LPI gets enabled. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3-its.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 47f2884..0d4b20d 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -376,6 +376,99 @@ static int its_handle_int(struct virt_its *its, uint64_t *cmdptr) return 0; } +/* + * For a given virtual LPI read the enabled bit and priority from the virtual + * property table and update the virtual IRQ's state in the given pending_irq. + */ +static int update_lpi_property(struct domain *d, uint32_t vlpi, + struct pending_irq *p) +{ + paddr_t addr; + uint8_t property; + int ret; + + addr = d->arch.vgic.rdist_propbase & GENMASK_ULL(51, 12); + + ret = vgic_access_guest_memory(d, addr + vlpi - LPI_OFFSET, + &property, sizeof(property), false); + if ( ret ) + return ret; + + p->lpi_priority = property & LPI_PROP_PRIO_MASK; + if ( property & LPI_PROP_ENABLED ) + set_bit(GIC_IRQ_GUEST_ENABLED, &p->status); + else + clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); + + return 0; +} + +/* + * For a given virtual LPI read the enabled bit and priority from the virtual + * property table and update the virtual IRQ's state. + * This takes care of removing or pushing of virtual LPIs to their VCPUs. + * Also check if this LPI is due to be injected and do it, if needed. + */ +static int update_lpi_enabled_status(struct domain *d, + struct vcpu *vcpu, uint32_t vlpi) +{ + struct pending_irq *p = d->arch.vgic.handler->lpi_to_pending(d, vlpi); + unsigned long flags; + int ret; + + if ( !p ) + return -EINVAL; + + spin_lock_irqsave(&vcpu->arch.vgic.lock, flags); + ret = update_lpi_property(d, vlpi, p); + if ( ret ) { + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + return ret; + } + + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + { + if ( !list_empty(&p->inflight) && + !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_raise_guest_irq(vcpu, vlpi, p->lpi_priority); + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + + /* Check whether the LPI has fired while the guest had it disabled. */ + if ( test_and_clear_bit(GIC_IRQ_GUEST_LPI_PENDING, &p->status) ) + vgic_vcpu_inject_irq(vcpu, vlpi); + } + else + { + clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + + gic_remove_from_queues(vcpu, vlpi); + } + + return 0; +} + +static int its_handle_inv(struct virt_its *its, uint64_t *cmdptr) +{ + uint32_t devid = its_cmd_get_deviceid(cmdptr); + uint32_t eventid = its_cmd_get_id(cmdptr); + struct vcpu *vcpu; + uint32_t vlpi; + + /* Translate the event into a vCPU/vLPI pair. */ + if ( !read_itte(its, devid, eventid, &vcpu, &vlpi) ) + return -1; + + /* + * Now read the property table and update our cached status. This + * also takes care if this LPI now needs to be injected or removed. + */ + if ( update_lpi_enabled_status(its->d, vcpu, vlpi) ) + return -1; + + return 0; +} + static int its_handle_mapc(struct virt_its *its, uint64_t *cmdptr) { uint32_t collid = its_cmd_get_collection(cmdptr); @@ -615,6 +708,9 @@ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its) case GITS_CMD_INT: ret = its_handle_int(its, command); break; + case GITS_CMD_INV: + ret = its_handle_inv(its, command); + break; case GITS_CMD_MAPC: ret = its_handle_mapc(its, command); break;