From patchwork Wed Apr 5 23:18:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9665907 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 57C2460352 for ; Wed, 5 Apr 2017 23:23:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49E672816B for ; Wed, 5 Apr 2017 23:23:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3ECDE28584; Wed, 5 Apr 2017 23:23:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D599B2816B for ; Wed, 5 Apr 2017 23:23:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cvuEL-0004SY-Vy; Wed, 05 Apr 2017 23:20:49 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cvuEK-0004Rp-PQ for xen-devel@lists.xenproject.org; Wed, 05 Apr 2017 23:20:48 +0000 Received: from [193.109.254.147] by server-11.bemta-6.messagelabs.com id 92/26-03642-0DB75E85; Wed, 05 Apr 2017 23:20:48 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTfd89dM Ig/nvZC2+b5nM5MDocfjDFZYAxijWzLyk/IoE1ozzW76zFHyUrWg7s421gfGPeBcjF4eQwCZG ibZLj9ggnL2MEk3fW1m6GDk52AR0JXbcfM0MYosIhErM+fkIyObgYBaolOhexA8SFhZwkDi8Z S4riM0ioCrx9PxfJhCbV8BNYu29+6wg5RICchJX/iWAhDkF3CVeth4Dmy4EVHJt4lSWCYzcCx gZVjFqFKcWlaUW6RqZ6CUVZaZnlOQmZuboGhqY6eWmFhcnpqfmJCYV6yXn525iBHqXAQh2MO7 7GHmIUZKDSUmUV8HnSYQQX1J+SmVGYnFGfFFpTmrxIUYZDg4lCV4+YLAICRalpqdWpGXmAMMM Ji3BwaMkwqsNkuYtLkjMLc5Mh0idYlSUEuflBUkIgCQySvPg2mChfYlRVkqYlxHoECGegtSi3 MwSVPlXjOIcjErCvFOqgKbwZOaVwE1/BbSYCWjxkzsPQRaXJCKkpBoYWTOuphndneg9c88B98 cmRVYblqUK7ma/0pZbl/jc/ErphS1ZzXfDJ3FOvJJ94ELa8gP9NZcf6XI/WPX2EduW4yd6rQT NjbR+XLCMjjP88bDfx30WR+Q7XbOJ6b431r7xke0vW3rB6RnbXo3AfXGcP/6UG0nPaeRRyObR v+ma1rl6do+IfmujEktxRqKhFnNRcSIAme9BMmgCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-5.tower-27.messagelabs.com!1491434446!90426292!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 56939 invoked from network); 5 Apr 2017 23:20:47 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-27.messagelabs.com with SMTP; 5 Apr 2017 23:20:47 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 93613344; Wed, 5 Apr 2017 16:20:46 -0700 (PDT) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 53B013F4FF; Wed, 5 Apr 2017 16:20:45 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 6 Apr 2017 00:18:59 +0100 Message-Id: <1491434362-30310-8-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1491434362-30310-1-git-send-email-andre.przywara@arm.com> References: <1491434362-30310-1-git-send-email-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Shanker Donthineni , Vijay Kilari Subject: [Xen-devel] [PATCH v5 07/30] ARM: GICv3 ITS: map ITS command buffer X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Instead of directly manipulating the tables in memory, an ITS driver sends commands via a ring buffer in normal system memory to the ITS h/w to create or alter the LPI mappings. Allocate memory for that buffer and tell the ITS about it to be able to send ITS commands. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v3-its.c | 53 ++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/gic_v3_its.h | 6 +++++ 2 files changed, 59 insertions(+) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index eef2933..d8e978a 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -20,10 +20,13 @@ #include #include +#include #include #include #include +#define ITS_CMD_QUEUE_SZ SZ_1M + /* * No lock here, as this list gets only populated upon boot while scanning * firmware tables for all host ITSes, and only gets iterated afterwards. @@ -60,6 +63,51 @@ static uint64_t encode_baser_phys_addr(paddr_t addr, unsigned int page_bits) return ret | ((addr & GENMASK_ULL(51, 48)) >> (48 - 12)); } +static void *its_map_cbaser(struct host_its *its) +{ + void __iomem *cbasereg = its->its_base + GITS_CBASER; + uint64_t reg; + void *buffer; + + reg = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT; + reg |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT; + reg |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT; + + buffer = _xzalloc(ITS_CMD_QUEUE_SZ, SZ_64K); + if ( !buffer ) + return NULL; + + if ( virt_to_maddr(buffer) & ~GENMASK_ULL(51, 12) ) + { + xfree(buffer); + return NULL; + } + + reg |= GITS_VALID_BIT | virt_to_maddr(buffer); + reg |= ((ITS_CMD_QUEUE_SZ / SZ_4K) - 1) & GITS_CBASER_SIZE_MASK; + writeq_relaxed(reg, cbasereg); + reg = readq_relaxed(cbasereg); + + /* If the ITS dropped shareability, drop cacheability as well. */ + if ( (reg & GITS_BASER_SHAREABILITY_MASK) == 0 ) + { + reg &= ~GITS_BASER_INNER_CACHEABILITY_MASK; + writeq_relaxed(reg, cbasereg); + } + + /* + * If the command queue memory is mapped as uncached, we need to flush + * it on every access. + */ + if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) + { + its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; + printk(XENLOG_WARNING "using non-cacheable ITS command queue\n"); + } + + return buffer; +} + /* The ITS BASE registers work with page sizes of 4K, 16K or 64K. */ #define BASER_PAGE_BITS(sz) ((sz) * 2 + 12) @@ -180,6 +228,11 @@ static int gicv3_its_init_single_its(struct host_its *hw_its) } } + hw_its->cmd_buf = its_map_cbaser(hw_its); + if ( !hw_its->cmd_buf ) + return -ENOMEM; + writeq_relaxed(0, hw_its->its_base + GITS_CWRITER); + return 0; } diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h index 6e51b98..a68ccf3 100644 --- a/xen/include/asm-arm/gic_v3_its.h +++ b/xen/include/asm-arm/gic_v3_its.h @@ -84,8 +84,12 @@ #define GITS_BASER_OUTER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) #define GITS_BASER_INNER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT) +#define GITS_CBASER_SIZE_MASK 0xff + #include +#define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) + /* data structure for each hardware ITS */ struct host_its { struct list_head entry; @@ -96,6 +100,8 @@ struct host_its { unsigned int devid_bits; unsigned int evid_bits; unsigned int itte_size; + void *cmd_buf; + unsigned int flags; };