From patchwork Wed Apr 12 00:44:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9676245 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A3C7060384 for ; Wed, 12 Apr 2017 00:48:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8A5CB2856B for ; Wed, 12 Apr 2017 00:48:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7F15D2858C; Wed, 12 Apr 2017 00:48:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E5B0B2856B for ; Wed, 12 Apr 2017 00:48:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cy6Qs-0001CT-Ko; Wed, 12 Apr 2017 00:46:50 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cy6Qr-00019S-HP for xen-devel@lists.xenproject.org; Wed, 12 Apr 2017 00:46:49 +0000 Received: from [193.109.254.147] by server-3.bemta-6.messagelabs.com id F5/78-27751-8F87DE85; Wed, 12 Apr 2017 00:46:48 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTfdHxds Ig59XhC2+b5nM5MDocfjDFZYAxijWzLyk/IoE1oz9rdcZCz6LV0x5eIC9gXG9UBcjF4eQwCZG iU8z37NBOHsZJWbt+87excjJwSagK7Hj5mtmEFtEIFRizs9HzCBFzAJrGCXaPz1lBUkIC5hLn OvqYuli5OBgEVCVuNAUCxLmFXCX6Pj0lxUkLCEgJ3HlXwJImBMovH33RLBOIQE3ia3TFjNPYO RewMiwilGjOLWoLLVI19BYL6koMz2jJDcxM0fX0MBMLze1uDgxPTUnMalYLzk/dxMj0L8MQLC D8cuygEOMkhxMSqK8lxXeRgjxJeWnVGYkFmfEF5XmpBYfYpTh4FCS4L1WDpQTLEpNT61Iy8wB BhpMWoKDR0mE9yJImre4IDG3ODMdInWKUVFKnLcUJCEAksgozYNrgwX3JUZZKWFeRqBDhHgKU otyM0tQ5V8xinMwKgnzCgBjRYgnM68EbvoroMVMQIvP7HoJsrgkESEl1cBY/95/fsyv5Ut1v1 ZZmjxv8Ndmn9kkpJyT6Lt3t9Laz153ndkXFt++9l5q0/nVl1ku7r/6Vd5iDfPxruvbeT73ctz eHOfd4Dsri+Po3g3664qyn23juv2ihdew+1i57NVg557tS9TF7/OqN0lsixPvfGAnYTr3l8va y0vXLhKr9K/b3iE6xTFJiaU4I9FQi7moOBEA+oZdZWkCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-11.tower-27.messagelabs.com!1491958007!66321570!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 18012 invoked from network); 12 Apr 2017 00:46:48 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-11.tower-27.messagelabs.com with SMTP; 12 Apr 2017 00:46:48 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 979F2CFC; Tue, 11 Apr 2017 17:46:47 -0700 (PDT) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DE8E03F575; Tue, 11 Apr 2017 17:46:45 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 12 Apr 2017 01:44:30 +0100 Message-Id: <1491957874-31600-24-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1491957874-31600-1-git-send-email-andre.przywara@arm.com> References: <1491957874-31600-1-git-send-email-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v8 23/27] ARM: vITS: handle INV command X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The INV command instructs the ITS to update the configuration data for a given LPI by re-reading its entry from the property table. We don't need to care so much about the priority value, but enabling or disabling an LPI has some effect: We remove or push virtual LPIs to their VCPUs, also check the virtual pending bit if an LPI gets enabled. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3-its.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 09cb3af..f2789c5 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -418,6 +418,68 @@ static int update_lpi_property(struct domain *d, uint32_t vlpi, return 0; } +/* + * Checks whether an LPI that got enabled or disabled needs to change + * something in the VGIC (added or removed from the LR or queues). + * Must be called with the VCPU VGIC lock held. + */ +static void update_lpi_vgic_status(struct vcpu *v, struct pending_irq *p, + uint32_t vlpi) +{ + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + { + if ( !list_empty(&p->inflight) && + !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_raise_guest_irq(v, vlpi, p->lpi_priority); + } + else + { + clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); + list_del_init(&p->lr_queue); + } +} + +static int its_handle_inv(struct virt_its *its, uint64_t *cmdptr) +{ + struct domain *d = its->d; + uint32_t devid = its_cmd_get_deviceid(cmdptr); + uint32_t eventid = its_cmd_get_id(cmdptr); + struct pending_irq *p; + unsigned long flags; + struct vcpu *vcpu; + uint32_t vlpi; + int ret = -1; + + /* Translate the event into a vCPU/vLPI pair. */ + if ( !read_itte(its, devid, eventid, &vcpu, &vlpi) ) + return -1; + + if ( vlpi == INVALID_LPI ) + return -1; + + spin_lock_irqsave(&vcpu->arch.vgic.lock, flags); + + p = d->arch.vgic.handler->lpi_to_pending(d, vlpi); + if ( !p ) + goto out_unlock; + + /* Read the property table and update our cached status. */ + if ( update_lpi_property(d, vlpi, p) ) + goto out_unlock; + + /* Check whether the LPI needs to go on a VCPU. */ + update_lpi_vgic_status(vcpu, p, vlpi); + + ret = 0; + +out_unlock: + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + + return ret; +} + static int its_handle_mapc(struct virt_its *its, uint64_t *cmdptr) { uint32_t collid = its_cmd_get_collection(cmdptr); @@ -757,6 +819,9 @@ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its) case GITS_CMD_INT: ret = its_handle_int(its, command); break; + case GITS_CMD_INV: + ret = its_handle_inv(its, command); + break; case GITS_CMD_MAPC: ret = its_handle_mapc(its, command); break;