From patchwork Wed Apr 12 00:44:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9676281 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 82A3F60383 for ; Wed, 12 Apr 2017 00:48:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 693CC28550 for ; Wed, 12 Apr 2017 00:48:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E0AA2857B; Wed, 12 Apr 2017 00:48:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E62C328550 for ; Wed, 12 Apr 2017 00:48:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cy6QL-0000QN-13; Wed, 12 Apr 2017 00:46:17 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cy6QJ-0000NO-K0 for xen-devel@lists.xenproject.org; Wed, 12 Apr 2017 00:46:15 +0000 Received: from [85.158.139.211] by server-15.bemta-5.messagelabs.com id 58/D5-01711-5D87DE85; Wed, 12 Apr 2017 00:46:13 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTfdixds Ig/b1Nhbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8bfb3+ZC5o0K16e+cXYwHhOoYuRi0NIYBOj xOf3e9ghnL2MEnPb9gE5nBxsAroSO26+ZgaxRQRCJeb8fMQMUsQssIZRov3TU9YuRg4OYaDE1 5WSIDUsAqoS23bMAavnFXCT2L5uGgtIiYSAnMSVfwkgYU4Bd4ntuyeygthCQCVbpy1mnsDIvY CRYRWjenFqUVlqka65XlJRZnpGSW5iZo6uoYGpXm5qcXFiempOYlKxXnJ+7iZGoHcZgGAH47H JzocYJTmYlER5Lyu8jRDiS8pPqcxILM6ILyrNSS0+xCjDwaEkwXutHCgnWJSanlqRlpkDDDOY tAQHj5IIryJImre4IDG3ODMdInWKUVFKnPduGVBCACSRUZoH1wYL7UuMslLCvIxAhwjxFKQW5 WaWoMq/YhTnYFQS5p0JMp4nM68EbvoroMVMQIvP7HoJsrgkESEl1cAo7VQy+bXccsaULc9nej vss1S9FVutXFcxe9msI8myRvEcfhYLCi538N+V97MsUnijpbPlW3cDi2pvxX2/r8vTHn5m+PD 0gX51S+2q0CZ9xpnMpXNPZERqnGxgSppTLLK8j6FIy79u+fn5fxeLux9h3im0Tr20YleY0rZr dxUS1mXd3p8deEyJpTgj0VCLuag4EQDkBGrIaAIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-10.tower-206.messagelabs.com!1491957969!71714519!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 58311 invoked from network); 12 Apr 2017 00:46:09 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-10.tower-206.messagelabs.com with SMTP; 12 Apr 2017 00:46:09 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5AC8B16; Tue, 11 Apr 2017 17:46:08 -0700 (PDT) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3EA113F575; Tue, 11 Apr 2017 17:46:07 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 12 Apr 2017 01:44:11 +0100 Message-Id: <1491957874-31600-5-git-send-email-andre.przywara@arm.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1491957874-31600-1-git-send-email-andre.przywara@arm.com> References: <1491957874-31600-1-git-send-email-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijaya Kumar K , Vijay Kilari , Shanker Donthineni Subject: [Xen-devel] [PATCH v8 04/27] ARM: GICv3: introduce separate pending_irq structs for LPIs X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP For the same reason that allocating a struct irq_desc for each possible LPI is not an option, having a struct pending_irq for each LPI is also not feasible. We only care about mapped LPIs, so we can get away with having struct pending_irq's only for them. Maintain a radix tree per domain where we drop the pointer to the respective pending_irq. The index used is the virtual LPI number. The memory for the actual structures has been allocated already per device at device mapping time. Teach the existing VGIC functions to find the right pointer when being given a virtual LPI number. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v2.c | 8 ++++++++ xen/arch/arm/vgic-v3.c | 23 +++++++++++++++++++++++ xen/arch/arm/vgic.c | 2 ++ xen/include/asm-arm/domain.h | 2 ++ xen/include/asm-arm/vgic.h | 2 ++ 5 files changed, 37 insertions(+) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index dc9f95b..0587569 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -702,10 +702,18 @@ static void vgic_v2_domain_free(struct domain *d) /* Nothing to be cleanup for this driver */ } +static struct pending_irq *vgic_v2_lpi_to_pending(struct domain *d, + unsigned int vlpi) +{ + /* Dummy function, no LPIs on a VGICv2. */ + BUG(); +} + static const struct vgic_ops vgic_v2_ops = { .vcpu_init = vgic_v2_vcpu_init, .domain_init = vgic_v2_domain_init, .domain_free = vgic_v2_domain_free, + .lpi_to_pending = vgic_v2_lpi_to_pending, .max_vcpus = 8, }; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index ebcca22..f462610 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1454,6 +1454,9 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.nr_regions = rdist_count; d->arch.vgic.rdist_regions = rdist_regions; + rwlock_init(&d->arch.vgic.pend_lpi_tree_lock); + radix_tree_init(&d->arch.vgic.pend_lpi_tree); + /* * Domain 0 gets the hardware address. * Guests get the virtual platform layout. @@ -1533,14 +1536,34 @@ static int vgic_v3_domain_init(struct domain *d) static void vgic_v3_domain_free(struct domain *d) { vgic_v3_its_free_domain(d); + radix_tree_destroy(&d->arch.vgic.pend_lpi_tree, NULL); xfree(d->arch.vgic.rdist_regions); } +/* + * Looks up a virtual LPI number in our tree of mapped LPIs. This will return + * the corresponding struct pending_irq, which we also use to store the + * enabled and pending bit plus the priority. + * Returns NULL if an LPI cannot be found (or no LPIs are supported). + */ +static struct pending_irq *vgic_v3_lpi_to_pending(struct domain *d, + unsigned int lpi) +{ + struct pending_irq *pirq; + + read_lock(&d->arch.vgic.pend_lpi_tree_lock); + pirq = radix_tree_lookup(&d->arch.vgic.pend_lpi_tree, lpi); + read_unlock(&d->arch.vgic.pend_lpi_tree_lock); + + return pirq; +} + static const struct vgic_ops v3_ops = { .vcpu_init = vgic_v3_vcpu_init, .domain_init = vgic_v3_domain_init, .domain_free = vgic_v3_domain_free, .emulate_reg = vgic_v3_emulate_reg, + .lpi_to_pending = vgic_v3_lpi_to_pending, /* * We use both AFF1 and AFF0 in (v)MPIDR. Thus, the max number of CPU * that can be supported is up to 4096(==256*16) in theory. diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index b9fc837..c2bfdb1 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -439,6 +439,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq) * are used for SPIs; the rests are used for per cpu irqs */ if ( irq < 32 ) n = &v->arch.vgic.pending_irqs[irq]; + else if ( is_lpi(irq) ) + n = v->domain->arch.vgic.handler->lpi_to_pending(v->domain, irq); else n = &v->domain->arch.vgic.pending_irqs[irq - 32]; return n; diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 7c3829d..3d8e84c 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -111,6 +111,8 @@ struct arch_domain uint32_t rdist_stride; /* Re-Distributor stride */ struct rb_root its_devices; /* Devices mapped to an ITS */ spinlock_t its_devices_lock; /* Protects the its_devices tree */ + struct radix_tree_root pend_lpi_tree; /* Stores struct pending_irq's */ + rwlock_t pend_lpi_tree_lock; /* Protects the pend_lpi_tree */ unsigned int intid_bits; #endif } vgic; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index df75064..c9075a9 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -134,6 +134,8 @@ struct vgic_ops { void (*domain_free)(struct domain *d); /* vGIC sysreg/cpregs emulate */ bool (*emulate_reg)(struct cpu_user_regs *regs, union hsr hsr); + /* lookup the struct pending_irq for a given LPI interrupt */ + struct pending_irq *(*lpi_to_pending)(struct domain *d, unsigned int vlpi); /* Maximum number of vCPU supported */ const unsigned int max_vcpus; };