From patchwork Thu May 18 05:34:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9733905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D546601BC for ; Thu, 18 May 2017 11:43:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B9F420952 for ; Thu, 18 May 2017 11:43:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 406192621D; Thu, 18 May 2017 11:43:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 67A0724560 for ; Thu, 18 May 2017 11:43:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJnK-0004Vg-K8; Thu, 18 May 2017 11:40:38 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJnI-0004TS-G0 for xen-devel@lists.xen.org; Thu, 18 May 2017 11:40:36 +0000 Received: from [193.109.254.147] by server-11.bemta-6.messagelabs.com id BE/81-03587-3388D195; Thu, 18 May 2017 11:40:35 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLLMWRWlGSWpSXmKPExsXS1tYhr2vcIRt psLed1WLJx8UsDoweR3f/ZgpgjGLNzEvKr0hgzbj7XLxgWkbF5AXXmBsYFwZ2MXJwCAlUSpya kN3FyMkhIcArcWTZDFYI21/iedsbli5GLqCSDkaJBRMbmUESbALqEicWT2QEsUUEpCWufb4MZ jML7GOUePNcFWSmsIC7xJ/lwSBhFgFVicaDM9lBbF4BV4k1vf3MEPMVJKY8fA9mcwLFt229xQ JiCwm4SDQu7GWdwMi7gJFhFaNGcWpRWWqRrqG5XlJRZnpGSW5iZo6uoYGZXm5qcXFiempOYlK xXnJ+7iZGYCAwAMEOxtsbAw4xSnIwKYnyHi6QjRTiS8pPqcxILM6ILyrNSS0+xCjDwaEkwcvX DpQTLEpNT61Iy8wBhiRMWoKDR0mEVwckzVtckJhbnJkOkTrFaMzxbumH90wcV1o/vmcSYsnLz 0uVEufd2AZUKgBSmlGaBzcIFiuXGGWlhHkZgU4T4ilILcrNLEGVf8UozsGoJMy7A2QhT2ZeCd y+V0CnMAGd0vxAGuSUkkSElFQDY7ncKa2j5oYXW8RObXnxfY/mik3VZU8+bThoHPDj61rXxRY 7tNbxPZGp3DLHWsF0kX2clJ3D9PoXk0MCOAMeX/1dLcOTd2a/aZLGvfW7A76tWbonbuaS5ESu 2l1p1iZTD7Mf7+6Xe+z89k71KuODv/YK9C/Iydnesrmmt+/fu9OCRuXbDt2Kz1RiKc5INNRiL ipOBADyeuejkAIAAA== X-Env-Sender: tianyu.lan@intel.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1495107632!90602768!1 X-Originating-IP: [134.134.136.31] X-SpamReason: No, hits=1.3 required=7.0 tests=BODY_RANDOM_LONG, DATE_IN_PAST_06_12,UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 29927 invoked from network); 18 May 2017 11:40:34 -0000 Received: from mga06.intel.com (HELO mga06.intel.com) (134.134.136.31) by server-14.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 18 May 2017 11:40:34 -0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP; 18 May 2017 04:40:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,358,1491289200"; d="scan'208";a="263417770" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.124]) by fmsmga004.fm.intel.com with ESMTP; 18 May 2017 04:40:30 -0700 From: Lan Tianyu To: xen-devel@lists.xen.org Date: Thu, 18 May 2017 01:34:41 -0400 Message-Id: <1495085696-10819-12-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> References: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> Cc: Lan Tianyu , kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, jbeulich@suse.com, Chao Gao Subject: [Xen-devel] [RFC PATCH V2 11/26] x86/hvm: Introduce a emulated VTD for HVM X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao This patch adds create/destroy/query function for the emulated VTD and adapts it to the common VIOMMU abstraction. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- xen/arch/x86/hvm/Makefile | 1 + xen/arch/x86/hvm/vvtd.c | 176 ++++++++++++++++++++++++++++++++++++ xen/drivers/passthrough/vtd/iommu.h | 102 ++++++++++++++++----- xen/include/asm-x86/viommu.h | 3 + 4 files changed, 259 insertions(+), 23 deletions(-) create mode 100644 xen/arch/x86/hvm/vvtd.c diff --git a/xen/arch/x86/hvm/Makefile b/xen/arch/x86/hvm/Makefile index 0a3d0f4..82a2030 100644 --- a/xen/arch/x86/hvm/Makefile +++ b/xen/arch/x86/hvm/Makefile @@ -22,6 +22,7 @@ obj-y += rtc.o obj-y += save.o obj-y += stdvga.o obj-y += vioapic.o +obj-y += vvtd.o obj-y += viridian.o obj-y += vlapic.o obj-y += vmsi.o diff --git a/xen/arch/x86/hvm/vvtd.c b/xen/arch/x86/hvm/vvtd.c new file mode 100644 index 0000000..e364f2b --- /dev/null +++ b/xen/arch/x86/hvm/vvtd.c @@ -0,0 +1,176 @@ +/* + * vvtd.c + * + * virtualize VTD for HVM. + * + * Copyright (C) 2017 Chao Gao, Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms and conditions of the GNU General Public + * License, version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this program; If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../../drivers/passthrough/vtd/iommu.h" + +struct hvm_hw_vvtd_regs { + uint8_t data[1024]; +}; + +/* Status field of struct vvtd */ +#define VIOMMU_STATUS_IRQ_REMAPPING_ENABLED (1 << 0) +#define VIOMMU_STATUS_DMA_REMAPPING_ENABLED (1 << 1) + +struct vvtd { + /* VIOMMU_STATUS_XXX_REMAPPING_ENABLED */ + int status; + /* Address range of remapping hardware register-set */ + uint64_t base_addr; + uint64_t length; + /* Point back to the owner domain */ + struct domain *domain; + struct hvm_hw_vvtd_regs *regs; + struct page_info *regs_page; +}; + +static inline void vvtd_set_reg(struct vvtd *vtd, uint32_t reg, + uint32_t value) +{ + *((uint32_t *)(&vtd->regs->data[reg])) = value; +} + +static inline uint32_t vvtd_get_reg(struct vvtd *vtd, uint32_t reg) +{ + return *((uint32_t *)(&vtd->regs->data[reg])); +} + +static inline uint8_t vvtd_get_reg_byte(struct vvtd *vtd, uint32_t reg) +{ + return *((uint8_t *)(&vtd->regs->data[reg])); +} + +#define vvtd_get_reg_quad(vvtd, reg, val) do { \ + (val) = vvtd_get_reg(vvtd, (reg) + 4 ); \ + (val) = (val) << 32; \ + (val) += vvtd_get_reg(vvtd, reg); \ +} while(0) +#define vvtd_set_reg_quad(vvtd, reg, val) do { \ + vvtd_set_reg(vvtd, reg, (val)); \ + vvtd_set_reg(vvtd, (reg) + 4, (val) >> 32); \ +} while(0) + +static void vvtd_reset(struct vvtd *vvtd, uint64_t capability) +{ + uint64_t cap, ecap; + + cap = DMA_CAP_NFR | DMA_CAP_SLLPS | DMA_CAP_FRO | \ + DMA_CAP_MGAW | DMA_CAP_SAGAW | DMA_CAP_ND; + ecap = DMA_ECAP_IR | DMA_ECAP_EIM | DMA_ECAP_QI; + vvtd_set_reg(vvtd, DMAR_VER_REG, 0x10UL); + vvtd_set_reg_quad(vvtd, DMAR_CAP_REG, cap); + vvtd_set_reg_quad(vvtd, DMAR_ECAP_REG, ecap); + vvtd_set_reg(vvtd, DMAR_GCMD_REG, 0); + vvtd_set_reg(vvtd, DMAR_GSTS_REG, 0); + vvtd_set_reg(vvtd, DMAR_RTADDR_REG, 0); + vvtd_set_reg_quad(vvtd, DMAR_CCMD_REG, 0x0ULL); + vvtd_set_reg(vvtd, DMAR_FSTS_REG, 0); + vvtd_set_reg(vvtd, DMAR_FECTL_REG, 0x80000000UL); + vvtd_set_reg(vvtd, DMAR_FEDATA_REG, 0); + vvtd_set_reg(vvtd, DMAR_FEADDR_REG, 0); + vvtd_set_reg(vvtd, DMAR_FEUADDR_REG, 0); + vvtd_set_reg(vvtd, DMAR_PMEN_REG, 0); + vvtd_set_reg_quad(vvtd, DMAR_IQH_REG, 0x0ULL); + vvtd_set_reg_quad(vvtd, DMAR_IQT_REG, 0x0ULL); + vvtd_set_reg_quad(vvtd, DMAR_IQA_REG, 0x0ULL); + vvtd_set_reg(vvtd, DMAR_ICS_REG, 0); + vvtd_set_reg(vvtd, DMAR_IECTL_REG, 0x80000000UL); + vvtd_set_reg(vvtd, DMAR_IEDATA_REG, 0); + vvtd_set_reg(vvtd, DMAR_IEADDR_REG, 0); + vvtd_set_reg(vvtd, DMAR_IEUADDR_REG, 0); + vvtd_set_reg(vvtd, DMAR_IRTA_REG, 0); +} + +static u64 vvtd_query_caps(struct domain *d) +{ + return VIOMMU_CAP_IRQ_REMAPPING; +} + +static int vvtd_create(struct domain *d, struct viommu *viommu) +{ + struct vvtd *vvtd; + int ret; + + if ( !is_hvm_domain(d) || (viommu->length != PAGE_SIZE) || + ((~vvtd_query_caps(d)) & viommu->caps) ) + return -EINVAL; + + ret = -ENOMEM; + vvtd = xmalloc_bytes(sizeof(struct vvtd)); + if ( vvtd == NULL ) + return ret; + + vvtd->regs_page = alloc_domheap_page(d, MEMF_no_owner); + if ( vvtd->regs_page == NULL ) + goto out1; + + vvtd->regs = __map_domain_page_global(vvtd->regs_page); + if ( vvtd->regs == NULL ) + goto out2; + clear_page(vvtd->regs); + + vvtd_reset(vvtd, viommu->caps); + vvtd->base_addr = viommu->base_address; + vvtd->length = viommu->length; + vvtd->domain = d; + vvtd->status = 0; + return 0; + +out2: + free_domheap_page(vvtd->regs_page); +out1: + xfree(vvtd); + return ret; +} + +static int vvtd_destroy(struct viommu *viommu) +{ + struct vvtd *vvtd = viommu->priv; + + if ( vvtd ) + { + unmap_domain_page_global(vvtd->regs); + free_domheap_page(vvtd->regs_page); + xfree(vvtd); + } + return 0; +} + +struct viommu_ops vvtd_hvm_vmx_ops = { + .query_caps = vvtd_query_caps, + .create = vvtd_create, + .destroy = vvtd_destroy +}; + +static int vvtd_register(void) +{ + viommu_register_type(VIOMMU_TYPE_INTEL_VTD, &vvtd_hvm_vmx_ops); + return 0; +} +__initcall(vvtd_register); diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index 72c1a2e..2e9dcaa 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -23,31 +23,54 @@ #include /* - * Intel IOMMU register specification per version 1.0 public spec. + * Intel IOMMU register specification per version 2.4 public spec. */ -#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ -#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ -#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ -#define DMAR_GCMD_REG 0x18 /* Global command register */ -#define DMAR_GSTS_REG 0x1c /* Global status register */ -#define DMAR_RTADDR_REG 0x20 /* Root entry table */ -#define DMAR_CCMD_REG 0x28 /* Context command reg */ -#define DMAR_FSTS_REG 0x34 /* Fault Status register */ -#define DMAR_FECTL_REG 0x38 /* Fault control register */ -#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ -#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ -#define DMAR_FEUADDR_REG 0x44 /* Upper address register */ -#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ -#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ -#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ -#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ -#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ -#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ -#define DMAR_IQH_REG 0x80 /* invalidation queue head */ -#define DMAR_IQT_REG 0x88 /* invalidation queue tail */ -#define DMAR_IQA_REG 0x90 /* invalidation queue addr */ -#define DMAR_IRTA_REG 0xB8 /* intr remap */ +#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ +#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ +#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ +#define DMAR_GCMD_REG 0x18 /* Global command register */ +#define DMAR_GSTS_REG 0x1c /* Global status register */ +#define DMAR_RTADDR_REG 0x20 /* Root entry table */ +#define DMAR_CCMD_REG 0x28 /* Context command reg */ +#define DMAR_FSTS_REG 0x34 /* Fault Status register */ +#define DMAR_FECTL_REG 0x38 /* Fault control register */ +#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ +#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ +#define DMAR_FEUADDR_REG 0x44 /* Upper address register */ +#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ +#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ +#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ +#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ +#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ +#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ +#define DMAR_IQH_REG 0x80 /* invalidation queue head */ +#define DMAR_IQT_REG 0x88 /* invalidation queue tail */ +#define DMAR_IQT_REG_HI 0x8c +#define DMAR_IQA_REG 0x90 /* invalidation queue addr */ +#define DMAR_IQA_REG_HI 0x94 +#define DMAR_ICS_REG 0x9c /* Invalidation complete status */ +#define DMAR_IECTL_REG 0xa0 /* Invalidation event control */ +#define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */ +#define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */ +#define DMAR_IEUADDR_REG 0xac /* Invalidation event address */ +#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr */ +#define DMAR_IRTA_REG_HI 0xbc +#define DMAR_PQH_REG 0xc0 /* Page request queue head */ +#define DMAR_PQH_REG_HI 0xc4 +#define DMAR_PQT_REG 0xc8 /* Page request queue tail*/ +#define DMAR_PQT_REG_HI 0xcc +#define DMAR_PQA_REG 0xd0 /* Page request queue address */ +#define DMAR_PQA_REG_HI 0xd4 +#define DMAR_PRS_REG 0xdc /* Page request status */ +#define DMAR_PECTL_REG 0xe0 /* Page request event control */ +#define DMAR_PEDATA_REG 0xe4 /* Page request event data */ +#define DMAR_PEADDR_REG 0xe8 /* Page request event address */ +#define DMAR_PEUADDR_REG 0xec /* Page event upper address */ +#define DMAR_MTRRCAP_REG 0x100 /* MTRR capability */ +#define DMAR_MTRRCAP_REG_HI 0x104 +#define DMAR_MTRRDEF_REG 0x108 /* MTRR default type */ +#define DMAR_MTRRDEF_REG_HI 0x10c #define OFFSET_STRIDE (9) #define dmar_readl(dmar, reg) readl((dmar) + (reg)) @@ -58,6 +81,31 @@ #define VER_MAJOR(v) (((v) & 0xf0) >> 4) #define VER_MINOR(v) ((v) & 0x0f) +/* CAP_REG */ +/* (offset >> 4) << 24 */ +#define DMA_DOMAIN_ID_SHIFT 16 /* 16-bit domain id for 64K domains */ +#define DMA_DOMAIN_ID_MASK ((1UL << DMA_DOMAIN_ID_SHIFT) - 1) +#define DMA_CAP_ND (((DMA_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL) +#define DMA_MGAW 39 /* Maximum Guest Address Width */ +#define DMA_CAP_MGAW (((DMA_MGAW - 1) & 0x3fULL) << 16) +#define DMA_MAMV 18ULL +#define DMA_CAP_MAMV (DMA_MAMV << 48) +#define DMA_CAP_PSI (1ULL << 39) +#define DMA_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) +#define DMAR_FRCD_REG_NR 1ULL +#define DMA_CAP_FRO_OFFSET 0x220ULL +#define DMA_CAP_FRO (DMA_CAP_FRO_OFFSET << 20) +#define DMA_CAP_NFR ((DMAR_FRCD_REG_NR - 1) << 40) + +/* Supported Adjusted Guest Address Widths */ +#define DMA_CAP_SAGAW_SHIFT 8 +#define DMA_CAP_SAGAW_MASK (0x1fULL << DMA_CAP_SAGAW_SHIFT) + /* 39-bit AGAW, 3-level page-table */ +#define DMA_CAP_SAGAW_39bit (0x2ULL << DMA_CAP_SAGAW_SHIFT) + /* 48-bit AGAW, 4-level page-table */ +#define DMA_CAP_SAGAW_48bit (0x4ULL << DMA_CAP_SAGAW_SHIFT) +#define DMA_CAP_SAGAW DMA_CAP_SAGAW_39bit + /* * Decoding Capability Register */ @@ -89,6 +137,14 @@ #define cap_afl(c) (((c) >> 3) & 1) #define cap_ndoms(c) (1 << (4 + 2 * ((c) & 0x7))) +/* ECAP_REG */ +/* (offset >> 4) << 8 */ +#define DMA_ECAP_QI (1ULL << 1) +/* Interrupt Remapping support */ +#define DMA_ECAP_IR (1ULL << 3) +#define DMA_ECAP_EIM (1ULL << 4) +#define DMA_ECAP_MHMV (15ULL << 20) + /* * Extended Capability Register */ diff --git a/xen/include/asm-x86/viommu.h b/xen/include/asm-x86/viommu.h index 1e8d4be..b730e65 100644 --- a/xen/include/asm-x86/viommu.h +++ b/xen/include/asm-x86/viommu.h @@ -22,6 +22,9 @@ #include #include +#include + +extern struct viommu_ops vvtd_hvm_vmx_ops; /* IRQ request type */ #define VIOMMU_REQUEST_IRQ_MSI 0