From patchwork Thu May 18 05:34:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9733861 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 21241601BC for ; Thu, 18 May 2017 11:42:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F57B20952 for ; Thu, 18 May 2017 11:42:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 03D19267EC; Thu, 18 May 2017 11:42:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 03E3120952 for ; Thu, 18 May 2017 11:42:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJns-0005Ni-1C; Thu, 18 May 2017 11:41:12 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dBJnq-0005Iv-AJ for xen-devel@lists.xen.org; Thu, 18 May 2017 11:41:10 +0000 Received: from [85.158.139.211] by server-15.bemta-5.messagelabs.com id B0/12-01730-5588D195; Thu, 18 May 2017 11:41:09 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsXS1tYhohvQIRt pcOmTjsWSj4tZHBg9ju7+zRTAGMWamZeUX5HAmjGr8SlbweWwimULjzA2MO6172Lk4hASmM4o sfZhJ2MXIyeHhACvxJFlM1ghbH+JdVfesEMUdTBK/Dqzmh0kwSagLnFi8USwBhEBaYlrny8zg hQxC/QwSkxc9oili5GDQ1jAR2LeUlOQGhYBVYnejQ+ZQcK8Aq4S1845QMxXkJjy8D0ziM0JFN 629RYLiC0k4CLRuLCXdQIj7wJGhlWMGsWpRWWpRbqGFnpJRZnpGSW5iZk5uoYGpnq5qcXFiem pOYlJxXrJ+bmbGIHhwAAEOxibtnseYpTkYFIS5T1cIBspxJeUn1KZkVicEV9UmpNafIhRhoND SYKXrx0oJ1iUmp5akZaZAwxMmLQEB4+SCO+aNqA0b3FBYm5xZjpE6hSjopQ470aQhABIIqM0D 64NFg2XGGWlhHkZgQ4R4ilILcrNLEGVf8UozsGoJMzLCrKdJzOvBG76K6DFTECLmx9IgywuSU RISTUwquxxcwuvm23ZmVTKc7dCKNc0ZJ/on0ONHlPdDiYvav9jLLLXdOr2X1qv93J4Lfb7+PO W0qUbhv/dpK9ay+7Ysb7yxMN7GxZkR90+/+PPBcXinEU7cj6vrt56VUBAW2xz+4PPPR/fTuSx uHthuf+xn/OLOiyOC98/8cn+4NlsrmnZtaKbxC6J+imxFGckGmoxFxUnAgBwDAfpgQIAAA== X-Env-Sender: tianyu.lan@intel.com X-Msg-Ref: server-7.tower-206.messagelabs.com!1495107662!96068433!1 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 9.4.12; banners=-,-,- X-VirusChecked: Checked Received: (qmail 46112 invoked from network); 18 May 2017 11:41:04 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-7.tower-206.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 18 May 2017 11:41:04 -0000 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 May 2017 04:41:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,358,1491289200"; d="scan'208";a="103583903" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.124]) by fmsmga005.fm.intel.com with ESMTP; 18 May 2017 04:41:00 -0700 From: Lan Tianyu To: xen-devel@lists.xen.org Date: Thu, 18 May 2017 01:34:54 -0400 Message-Id: <1495085696-10819-25-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> References: <1495085696-10819-1-git-send-email-tianyu.lan@intel.com> Cc: Lan Tianyu , andrew.cooper3@citrix.com, kevin.tian@intel.com, jbeulich@suse.com, Chao Gao Subject: [Xen-devel] [RFC PATCH V2 24/26] x86/vvtd: Add queued invalidation (QI) support X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao Queued Invalidation Interface is an expanded invalidation interface with extended capabilities. Hardware implementations report support for queued invalidation interface through the Extended Capability Register. The queued invalidation interface uses an Invalidation Queue (IQ), which is a circular buffer in system memory. Software submits commands by writing Invalidation Descriptors to the IQ. In this patch, a new function viommu_process_iq() is used for emulating how hardware handles invalidation requests through QI. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- xen/arch/x86/hvm/vvtd.c | 244 ++++++++++++++++++++++++++++++++++++ xen/drivers/passthrough/vtd/iommu.h | 29 ++++- 2 files changed, 272 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/vvtd.c b/xen/arch/x86/hvm/vvtd.c index a741452..ce25a77 100644 --- a/xen/arch/x86/hvm/vvtd.c +++ b/xen/arch/x86/hvm/vvtd.c @@ -427,6 +427,185 @@ static int vvtd_record_fault(struct vvtd *vvtd, return X86EMUL_OKAY; } +/* + * Process a invalidation descriptor. Currently, only Two types descriptors, + * Interrupt Entry Cache invalidation descritor and Invalidation Wait + * Descriptor are handled. + * @vvtd: the virtual vtd instance + * @i: the index of the invalidation descriptor to be processed + * + * If success return 0, or return -1 when failure. + */ +static int process_iqe(struct vvtd *vvtd, int i) +{ + uint64_t iqa, addr; + struct qinval_entry *qinval_page; + void *pg; + int ret; + + vvtd_get_reg_quad(vvtd, DMAR_IQA_REG, iqa); + ret = map_guest_page(vvtd->domain, DMA_IQA_ADDR(iqa)>>PAGE_SHIFT, + (void**)&qinval_page); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Can't map guest IRT (rc %d)", ret); + return -1; + } + + switch ( qinval_page[i].q.inv_wait_dsc.lo.type ) + { + case TYPE_INVAL_WAIT: + if ( qinval_page[i].q.inv_wait_dsc.lo.sw ) + { + addr = (qinval_page[i].q.inv_wait_dsc.hi.saddr << 2); + ret = map_guest_page(vvtd->domain, addr >> PAGE_SHIFT, &pg); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Can't map guest memory to inform guest " + "IWC completion (rc %d)", ret); + goto error; + } + *(uint32_t *)((uint64_t)pg + (addr & ~PAGE_MASK)) = + qinval_page[i].q.inv_wait_dsc.lo.sdata; + unmap_guest_page(pg); + } + + /* + * The following code generates an invalidation completion event + * indicating the invalidation wait descriptor completion. Note that + * the following code fragment is not tested properly. + */ + if ( qinval_page[i].q.inv_wait_dsc.lo.iflag ) + { + uint32_t ie_data, ie_addr; + if ( !vvtd_test_and_set_bit(vvtd, DMAR_ICS_REG, DMA_ICS_IWC_BIT) ) + { + __vvtd_set_bit(vvtd, DMAR_IECTL_REG, DMA_IECTL_IP_BIT); + if ( !vvtd_test_bit(vvtd, DMAR_IECTL_REG, DMA_IECTL_IM_BIT) ) + { + ie_data = vvtd_get_reg(vvtd, DMAR_IEDATA_REG); + ie_addr = vvtd_get_reg(vvtd, DMAR_IEADDR_REG); + vvtd_generate_interrupt(vvtd, ie_addr, ie_data); + __vvtd_clear_bit(vvtd, DMAR_IECTL_REG, DMA_IECTL_IP_BIT); + } + } + } + break; + + case TYPE_INVAL_IEC: + /* + * Currently, no cache is preserved in hypervisor. Only need to update + * pIRTEs which are modified in binding process. + */ + break; + + default: + goto error; + } + + unmap_guest_page((void*)qinval_page); + return 0; + +error: + unmap_guest_page((void*)qinval_page); + gdprintk(XENLOG_ERR, "Internal error in Queue Invalidation.\n"); + domain_crash(vvtd->domain); + return -1; +} + +/* + * Invalidate all the descriptors in Invalidation Queue. + */ +static void vvtd_process_iq(struct vvtd *vvtd) +{ + uint64_t iqh, iqt, iqa, max_entry, i; + int ret = 0; + + /* + * No new descriptor is fetched from the Invalidation Queue until + * software clears the IQE field in the Fault Status Register + */ + if ( vvtd_test_bit(vvtd, DMAR_FSTS_REG, DMA_FSTS_IQE_BIT) ) + return; + + vvtd_get_reg_quad(vvtd, DMAR_IQH_REG, iqh); + vvtd_get_reg_quad(vvtd, DMAR_IQT_REG, iqt); + vvtd_get_reg_quad(vvtd, DMAR_IQA_REG, iqa); + + max_entry = DMA_IQA_ENTRY_PER_PAGE << DMA_IQA_QS(iqa); + iqh = DMA_IQH_QH(iqh); + iqt = DMA_IQT_QT(iqt); + + ASSERT(iqt < max_entry); + if ( iqh == iqt ) + return; + + i = iqh; + while ( i != iqt ) + { + ret = process_iqe(vvtd, i); + if ( ret ) + break; + else + i = (i + 1) % max_entry; + vvtd_set_reg_quad(vvtd, DMAR_IQH_REG, i << DMA_IQH_QH_SHIFT); + } + + /* + * When IQE set, IQH references the desriptor associated with the error. + */ + if ( ret ) + vvtd_report_non_recoverable_fault(vvtd, DMA_FSTS_IQE_BIT); +} + +static int vvtd_write_iqt(struct vvtd *vvtd, unsigned long val) +{ + uint64_t iqa; + + if ( val & DMA_IQT_RSVD ) + { + VVTD_DEBUG(VVTD_DBG_RW, "Attempt to set reserved bits in " + "Invalidation Queue Tail."); + return X86EMUL_OKAY; + } + + vvtd_get_reg_quad(vvtd, DMAR_IQA_REG, iqa); + if ( DMA_IQT_QT(val) >= DMA_IQA_ENTRY_PER_PAGE << DMA_IQA_QS(iqa) ) + { + VVTD_DEBUG(VVTD_DBG_RW, "IQT: Value %lx exceeded supported max " + "index.", val); + return X86EMUL_OKAY; + } + + vvtd_set_reg_quad(vvtd, DMAR_IQT_REG, val); + vvtd_process_iq(vvtd); + return X86EMUL_OKAY; +} + +static int vvtd_write_iqa(struct vvtd *vvtd, unsigned long val) +{ + if ( val & DMA_IQA_RSVD ) + { + VVTD_DEBUG(VVTD_DBG_RW, "Attempt to set reserved bits in " + "Invalidation Queue Address."); + return X86EMUL_OKAY; + } + + vvtd_set_reg_quad(vvtd, DMAR_IQA_REG, val); + return X86EMUL_OKAY; +} + +static int vvtd_write_ics(struct vvtd *vvtd, uint32_t val) +{ + if ( val & DMA_ICS_IWC ) + { + __vvtd_clear_bit(vvtd, DMAR_ICS_REG, DMA_ICS_IWC_BIT); + /*When IWC field is cleared, the IP field needs to be cleared */ + __vvtd_clear_bit(vvtd, DMAR_IECTL_REG, DMA_IECTL_IP_BIT); + } + return X86EMUL_OKAY; +} + static int vvtd_write_frcd3(struct vvtd *vvtd, uint32_t val) { /* Writing a 1 means clear fault */ @@ -438,6 +617,29 @@ static int vvtd_write_frcd3(struct vvtd *vvtd, uint32_t val) return X86EMUL_OKAY; } +static int vvtd_write_iectl(struct vvtd *vvtd, uint32_t val) +{ + /* + * Only DMA_IECTL_IM bit is writable. Generate pending event when unmask. + */ + if ( !(val & DMA_IECTL_IM) ) + { + /* Clear IM and clear IP */ + __vvtd_clear_bit(vvtd, DMAR_IECTL_REG, DMA_IECTL_IM_BIT); + if ( vvtd_test_and_clear_bit(vvtd, DMAR_IECTL_REG, DMA_IECTL_IP_BIT) ) + { + uint32_t ie_data, ie_addr; + ie_data = vvtd_get_reg(vvtd, DMAR_IEDATA_REG); + ie_addr = vvtd_get_reg(vvtd, DMAR_IEADDR_REG); + vvtd_generate_interrupt(vvtd, ie_addr, ie_data); + } + } + else + __vvtd_set_bit(vvtd, DMAR_IECTL_REG, DMA_IECTL_IM_BIT); + + return X86EMUL_OKAY; +} + static int vvtd_write_fectl(struct vvtd *vvtd, uint32_t val) { /* @@ -480,6 +682,10 @@ static int vvtd_write_fsts(struct vvtd *vvtd, uint32_t val) if ( !((vvtd_get_reg(vvtd, DMAR_FSTS_REG) & DMA_FSTS_FAULTS)) ) __vvtd_clear_bit(vvtd, DMAR_FECTL_REG, DMA_FECTL_IP_BIT); + /* Continue to deal invalidation when IQE is clear */ + if ( !vvtd_test_bit(vvtd, DMAR_FSTS_REG, DMA_FSTS_IQE_BIT) ) + vvtd_process_iq(vvtd); + return X86EMUL_OKAY; } @@ -640,6 +846,36 @@ static int vvtd_write(struct vcpu *v, unsigned long addr, ret = vvtd_write_frcd3(vvtd, val); break; + case DMAR_IECTL_REG: + ret = vvtd_write_iectl(vvtd, val); + break; + + case DMAR_ICS_REG: + ret = vvtd_write_ics(vvtd, val); + break; + + case DMAR_IQT_REG: + ret = vvtd_write_iqt(vvtd, (uint32_t)val); + break; + + case DMAR_IQA_REG: + { + uint32_t iqa_hi; + + iqa_hi = vvtd_get_reg(vvtd, DMAR_IQA_REG_HI); + ret = vvtd_write_iqa(vvtd, (uint32_t)val | ((uint64_t)iqa_hi << 32)); + break; + } + + case DMAR_IQA_REG_HI: + { + uint32_t iqa_lo; + + iqa_lo = vvtd_get_reg(vvtd, DMAR_IQA_REG); + ret = vvtd_write_iqa(vvtd, (val << 32) | iqa_lo); + break; + } + case DMAR_IEDATA_REG: case DMAR_IEADDR_REG: case DMAR_IEUADDR_REG: @@ -670,6 +906,14 @@ static int vvtd_write(struct vcpu *v, unsigned long addr, ret = vvtd_write_frcd3(vvtd, val >> 32); break; + case DMAR_IQT_REG: + ret = vvtd_write_iqt(vvtd, val); + break; + + case DMAR_IQA_REG: + ret = vvtd_write_iqa(vvtd, val); + break; + default: ret = X86EMUL_UNHANDLEABLE; break; diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index 5474c72..135c4cf 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -207,6 +207,32 @@ #define DMA_IRTA_S(val) (val & 0xf) #define DMA_IRTA_SIZE(val) (1UL << (DMA_IRTA_S(val) + 1)) +/* IQH_REG */ +#define DMA_IQH_QH_SHIFT 4 +#define DMA_IQH_QH(val) ((val >> 4) & 0x7fffULL) + +/* IQT_REG */ +#define DMA_IQT_QT_SHIFT 4 +#define DMA_IQT_QT(val) ((val >> 4) & 0x7fffULL) +#define DMA_IQT_RSVD 0xfffffffffff80007ULL + +/* IQA_REG */ +#define DMA_MGAW 39 /* Maximum Guest Address Width */ +#define DMA_IQA_ADDR(val) (val & ~0xfffULL) +#define DMA_IQA_QS(val) (val & 0x7) +#define DMA_IQA_ENTRY_PER_PAGE (1 << 8) +#define DMA_IQA_RSVD (~((1ULL << DMA_MGAW) -1 ) | 0xff8ULL) + +/* IECTL_REG */ +#define DMA_IECTL_IM_BIT 31 +#define DMA_IECTL_IM (1 << DMA_IECTL_IM_BIT) +#define DMA_IECTL_IP_BIT 30 +#define DMA_IECTL_IP (((u64)1) << DMA_IECTL_IP_BIT) + +/* ICS_REG */ +#define DMA_ICS_IWC_BIT 0 +#define DMA_ICS_IWC (1 << DMA_ICS_IWC_BIT) + /* PMEN_REG */ #define DMA_PMEN_EPM (((u32)1) << 31) #define DMA_PMEN_PRS (((u32)1) << 0) @@ -241,7 +267,8 @@ #define DMA_FSTS_PPF (1U << DMA_FSTS_PPF_BIT) #define DMA_FSTS_AFO (1U << 2) #define DMA_FSTS_APF (1U << 3) -#define DMA_FSTS_IQE (1U << 4) +#define DMA_FSTS_IQE_BIT 4 +#define DMA_FSTS_IQE (1U << DMA_FSTS_IQE_BIT) #define DMA_FSTS_ICE (1U << 5) #define DMA_FSTS_ITE (1U << 6) #define DMA_FSTS_PRO_BIT 7