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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id g23sm55221109pfb.54.2017.06.06.03.05.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Jun 2017 03:05:02 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Tue, 6 Jun 2017 15:34:57 +0530 Message-Id: <1496743497-16087-1-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 Cc: Wei Liu , Julien Grall , Stefano Stabellini , Ian Jackson Subject: [Xen-devel] [PATCH 13/14 v4] xen/arm: vpl011: Add a pl011 uart DT node in the guest device tree X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The SBSA uart node format is as specified in Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt and given below: ARM SBSA defined generic UART ------------------------------ This UART uses a subset of the PL011 registers and consequently lives in the PL011 driver. It's baudrate and other communication parameters cannot be adjusted at runtime, so it lacks a clock specifier here. Required properties: - compatible: must be "arm,sbsa-uart" - reg: exactly one register range - interrupts: exactly one interrupt specifier - current-speed: the (fixed) baud rate set by the firmware Currently the baud rate of 115200 has been selected as a default value, which is one of the valid baud rate setttings. Higher baud rate was selected since an emulated pl011 can support any valid baud rate without any limitation of the hardware. Signed-off-by: Bhupinder Thakur Reviewed-by: Stefano Stabellini --- tools/libxl/libxl_arm.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index b60dfa9..b59fd9f 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -44,10 +44,22 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, uint32_t nr_spis = 0; unsigned int i; + /* + * If pl011 vuart is enabled then increment the nr_spis to allow allocation + * of SPI VIRQ for pl011. + */ + if (d_config->b_info.arch_arm.vuart) + nr_spis += (GUEST_VPL011_SPI - 32) + 1; + for (i = 0; i < d_config->b_info.num_irqs; i++) { uint32_t irq = d_config->b_info.irqs[i]; uint32_t spi; + if (d_config->b_info.arch_arm.vuart && (irq == GUEST_VPL011_SPI)) { + LOG(ERROR, "Physical IRQ %u conflicting with pl011 SPI\n", irq); + return ERROR_FAIL; + } + if (irq < 32) continue; @@ -149,9 +161,10 @@ static struct arch_info { const char *guest_type; const char *timer_compat; const char *cpu_compat; + const char *uart_compat; } arch_info[] = { - {"xen-3.0-armv7l", "arm,armv7-timer", "arm,cortex-a15" }, - {"xen-3.0-aarch64", "arm,armv8-timer", "arm,armv8" }, + {"xen-3.0-armv7l", "arm,armv7-timer", "arm,cortex-a15", "arm,sbsa-uart" }, + {"xen-3.0-aarch64", "arm,armv8-timer", "arm,armv8", "arm,sbsa-uart" }, }; /* @@ -609,6 +622,38 @@ static int make_hypervisor_node(libxl__gc *gc, void *fdt, return 0; } +static int make_vpl011_uart_node(libxl__gc *gc, void *fdt, + const struct arch_info *ainfo, + struct xc_dom_image *dom) +{ + int res; + gic_interrupt intr; + + res = fdt_begin_node(fdt, "sbsa-pl011"); + if (res) return res; + + res = fdt_property_compat(gc, fdt, 1, ainfo->uart_compat); + if (res) return res; + + res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, + 1, + GUEST_PL011_BASE, GUEST_PL011_SIZE); + if (res) return res; + + set_interrupt(intr, GUEST_VPL011_SPI, 0xf, DT_IRQ_TYPE_LEVEL_HIGH); + + res = fdt_property_interrupts(gc, fdt, &intr, 1); + if (res) return res; + + /* Use a default baud rate of 115200. */ + fdt_property_u32(fdt, "current-speed", 115200); + + res = fdt_end_node(fdt); + if (res) return res; + + return 0; +} + static const struct arch_info *get_arch_info(libxl__gc *gc, const struct xc_dom_image *dom) { @@ -908,6 +953,9 @@ next_resize: FDT( make_timer_node(gc, fdt, ainfo, xc_config->clock_frequency) ); FDT( make_hypervisor_node(gc, fdt, vers) ); + if (info->arch_arm.vuart) + FDT( make_vpl011_uart_node(gc, fdt, ainfo, dom) ); + if (pfdt) FDT( copy_partial_fdt(gc, fdt, pfdt) );