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See http://domainkeys.sourceforge.net/ DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=bitdefender.com; b=Zm1tAZNM3YLNXSwukPIScXmsKyjQrIZJvkCFqccUdPOjolvmgXDMyd//VGUSbkNX1lmaql/rZOcp+ED79twvI+Ns5ddDAJpkkT331nGWxXb/Ad6tJqFDKxMBia3KgYSFYEi5nVWLZdlyru4pGpCbxzMQGNkd+iNlpIvaopf6uoiJT8sxY2d3GNVSJco0AUYR9vuNDRWDClIeNVS8xNxB5QwFOPqVKzzvyJUy2rFwBiL8Pj7R0SuFtbTfCr5+7jl3h61ba44BoSYT7ESaKiO7aXk5MnJU1WHo6ez2f7CQqp9c/gsRdLw5IKArAIWuGjBQZ5cW/5SfyTbFY7zuWOJ8xw==; h=Received:Received:Received:Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:In-Reply-To:References; DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=bitdefender.com; h=from:to :cc:subject:date:message-id:in-reply-to:references; s=default; bh=G3l9qNXTLhk/XThlPrt1579MG4Q=; b=mCm+nHSvLwX7rPbaMU8VbkNw9Sjz HNOEbQYloYEp78t0aKBIguno7Qvq4NG6Na+OWiCiho1BuAe3+yQgNw+uPkUTfdq2 slQ6wRkXHIGEMmUPtwa6Bbn/qVDmrDh0PRatvu+TrqSoRA/LLohO36knmIWyrX6Y FhNvqT/2MhsW0vwHcdBcYCt0QFNYhgFzXkH4M6Pni2fm9EYFtkVLEeREEezV+XPt qezJzalCsiqh44TlIQZSAmVJ2vUchAjnQ2w83GksHwOex/UOIgQkzYS4kXRjZ4Ku J0k+y+LL6zMUAQqDze5gWv6FTDALJfbv+HN2U2XSysVu/JpaQoXAvW+WXQ== Received: (qmail 17787 invoked from network); 16 Jun 2017 22:20:26 +0300 Received: from mx01robo.bbu.dsd.mx.bitdefender.com (10.17.80.60) by mx02.buh.bitdefender.com with AES128-GCM-SHA256 encrypted SMTP; 16 Jun 2017 22:20:26 +0300 Received: (qmail 9493 invoked from network); 16 Jun 2017 22:20:26 +0300 Received: from unknown (HELO pepi-OptiPlex-9020.dsd.bitdefender.biz) (10.10.194.146) by mx01robo.bbu.dsd.mx.bitdefender.com with SMTP; 16 Jun 2017 22:20:26 +0300 From: Petre Pircalabu To: xen-devel@lists.xen.org Date: Fri, 16 Jun 2017 22:20:22 +0300 Message-Id: <1497640822-7741-3-git-send-email-ppircalabu@bitdefender.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497640822-7741-1-git-send-email-ppircalabu@bitdefender.com> References: <1496137567-6574-1-git-send-email-ppircalabu@bitdefender.com> <1497640822-7741-1-git-send-email-ppircalabu@bitdefender.com> Cc: Petre Pircalabu , tamas@tklengyel.com, wei.liu2@citrix.com, rcojocaru@bitdefender.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, jbeulich@suse.com Subject: [Xen-devel] [PATCH v3 2/2] xen-access: write_ctrlreg_c4 test X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add test for write_ctrlreg event handling. Signed-off-by: Petre Pircalabu --- tools/tests/xen-access/xen-access.c | 53 ++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/tools/tests/xen-access/xen-access.c b/tools/tests/xen-access/xen-access.c index 238011e..bbf5047 100644 --- a/tools/tests/xen-access/xen-access.c +++ b/tools/tests/xen-access/xen-access.c @@ -57,6 +57,13 @@ #define X86_TRAP_DEBUG 1 #define X86_TRAP_INT3 3 +/* From xen/include/asm-x86/x86-defns.h */ +#define X86_CR4_PGE 0x00000080 /* enable global pages */ + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + typedef struct vm_event { domid_t domain_id; xenevtchn_handle *xce_handle; @@ -314,6 +321,24 @@ static void get_request(vm_event_t *vm_event, vm_event_request_t *req) } /* + * X86 control register names + */ +static const char* get_x86_ctrl_reg_name(uint32_t index) +{ + static const char* names[] = { + [VM_EVENT_X86_CR0] = "CR0", + [VM_EVENT_X86_CR3] = "CR3", + [VM_EVENT_X86_CR4] = "CR4", + [VM_EVENT_X86_XCR0] = "XCR0", + }; + + if ( index > ARRAY_SIZE(names) || names[index] == NULL ) + return ""; + + return names[index]; +} + +/* * Note that this function is not thread safe. */ static void put_response(vm_event_t *vm_event, vm_event_response_t *rsp) @@ -337,7 +362,7 @@ void usage(char* progname) { fprintf(stderr, "Usage: %s [-m] write|exec", progname); #if defined(__i386__) || defined(__x86_64__) - fprintf(stderr, "|breakpoint|altp2m_write|altp2m_exec|debug|cpuid|desc_access"); + fprintf(stderr, "|breakpoint|altp2m_write|altp2m_exec|debug|cpuid|desc_access|write_ctrlreg_cr4"); #elif defined(__arm__) || defined(__aarch64__) fprintf(stderr, "|privcall"); #endif @@ -369,6 +394,7 @@ int main(int argc, char *argv[]) int debug = 0; int cpuid = 0; int desc_access = 0; + int write_ctrlreg_cr4 = 1; uint16_t altp2m_view_id = 0; char* progname = argv[0]; @@ -439,6 +465,10 @@ int main(int argc, char *argv[]) { desc_access = 1; } + else if ( !strcmp(argv[0], "write_ctrlreg_cr4") ) + { + write_ctrlreg_cr4 = 1; + } #elif defined(__arm__) || defined(__aarch64__) else if ( !strcmp(argv[0], "privcall") ) { @@ -596,6 +626,18 @@ int main(int argc, char *argv[]) } } + if ( write_ctrlreg_cr4 ) + { + /* Mask the CR4.PGE bit so no events will be generated for global TLB flushes. */ + rc = xc_monitor_write_ctrlreg(xch, domain_id, VM_EVENT_X86_CR4, 1, 1, + X86_CR4_PGE, 1); + if ( rc < 0 ) + { + ERROR("Error %d setting write control register trapping with vm_event\n", rc); + goto exit; + } + } + /* Wait for access */ for (;;) { @@ -806,6 +848,15 @@ int main(int argc, char *argv[]) req.u.desc_access.is_write); rsp.flags |= VM_EVENT_FLAG_EMULATE; break; + case VM_EVENT_REASON_WRITE_CTRLREG: + printf("Control register written: rip=%016"PRIx64", vcpu %d: " + "reg=%s, old_value=%016"PRIx64", new_value=%016"PRIx64"\n", + req.data.regs.x86.rip, + req.vcpu_id, + get_x86_ctrl_reg_name(req.u.write_ctrlreg.index), + req.u.write_ctrlreg.old_value, + req.u.write_ctrlreg.new_value); + break; default: fprintf(stderr, "UNKNOWN REASON CODE %d\n", req.reason); }