From patchwork Sat Jul 15 00:31:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 9841835 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1EA24603F3 for ; Sat, 15 Jul 2017 00:48:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F46A287AE for ; Sat, 15 Jul 2017 00:48:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0423D287B4; Sat, 15 Jul 2017 00:48:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 92A46287AE for ; Sat, 15 Jul 2017 00:48:32 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dWBEZ-0007cY-Lr; Sat, 15 Jul 2017 00:46:59 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dWBEY-0007WG-Ax for xen-devel@lists.xenproject.org; Sat, 15 Jul 2017 00:46:58 +0000 Received: from [85.158.137.68] by server-8.bemta-3.messagelabs.com id 84/06-02176-CE569695; Sat, 15 Jul 2017 00:46:36 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRWlGSWpSXmKPExsVywNxEW/d1ama kwc6LKhbft0xmcmD0OPzhCksAYxRrZl5SfkUCa8aMY5dYC75ZV/y7+pSlgXGzbhcjJ4eQQIXE mmuvmUBsCQFeiSPLZrBC2P4SX9p2MUHUNDBKzD6lDGKzCahLPP7aAxYXEVCSuLdqMpDNxcEsM J9J4vX5B8xdjBwcwgIOEms6c0FqWARUJW70PGQDsXkFPCQePX0ENV9O4uSxyWA2J1B86r42dp BWIQF3iZbZ5RMYeRcwMqxi1ChOLSpLLdI1NtBLKspMzyjJTczM0TU0MNbLTS0uTkxPzUlMKtZ Lzs/dxAgMhXoGBsYdjJ0n/A4xSnIwKYnyvrudESnEl5SfUpmRWJwRX1Sak1p8iFGGg0NJgpcf GFpCgkWp6akVaZk5wKCESUtw8CiJ8M5KAUrzFhck5hZnpkOkTjHqcrya8P8bkxBLXn5eqpQ47 ymQIgGQoozSPLgRsAi5xCgrJczLyMDAIMRTkFqUm1mCKv+KUZyDUUmYdz7IFJ7MvBK4Ta+Ajm ACOqItKwPkiJJEhJRUA+OsxtrPiw4s1nEpYHJ/LSJ4u+zdgyiT1tDSphliodvYjKW2+3qwlsc 9Vbwx0Xlxt9ak/Wd5TFhWiqWxz3RuU83sF5kzN9fnX8qq70v7BNomOWtcZuHYc2mR14zDtifF DJhPV95n2/5ar8u9VseN5Wbi5KezHtmZn56x482E4tgYb4/MZSJqgkosxRmJhlrMRcWJAKIE2 HGLAgAA X-Env-Sender: yi.y.sun@linux.intel.com X-Msg-Ref: server-6.tower-31.messagelabs.com!1500079549!66978060!17 X-Originating-IP: [192.55.52.43] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.4.25; banners=-,-,- X-VirusChecked: Checked Received: (qmail 37893 invoked from network); 15 Jul 2017 00:46:35 -0000 Received: from mga05.intel.com (HELO mga05.intel.com) (192.55.52.43) by server-6.tower-31.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 15 Jul 2017 00:46:35 -0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP; 14 Jul 2017 17:46:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,360,1496127600"; d="scan'208";a="111534906" Received: from vmmmba-s2600wft.bj.intel.com ([10.240.193.80]) by orsmga002.jf.intel.com with ESMTP; 14 Jul 2017 17:46:31 -0700 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Sat, 15 Jul 2017 08:31:49 +0800 Message-Id: <1500078716-5928-17-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500078716-5928-1-git-send-email-yi.y.sun@linux.intel.com> References: <1500078716-5928-1-git-send-email-yi.y.sun@linux.intel.com> Cc: kevin.tian@intel.com, wei.liu2@citrix.com, andrew.cooper3@citrix.com, dario.faggioli@citrix.com, ian.jackson@eu.citrix.com, Yi Sun , mengxu@cis.upenn.edu, jbeulich@suse.com, chao.p.peng@linux.intel.com, roger.pau@citrix.com Subject: [Xen-devel] [PATCH v14 16/23] x86: L2 CAT: implement CPU init flow. X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements the CPU init flow for L2 CAT. Signed-off-by: Yi Sun Reviewed-by: Jan Beulich --- v14: - remove the 'Notes' in commit message because a stub function is implemented to avoid the potential issue. (suggested by Jan Beulich) - put address of 'feat_l2_cat' back to it if 'cat_init_feature()' fails to avoid leakage. (suggested by Jan Beulich) - change 'feat_name' to 'cat_feat_name' and move it into 'cat_init_feature()' which is the only caller. (suggested by Jan Beulich) - register the callback functions into 'l2_cat_props' to avoid crash if user does not apply later patches. (suggested by Jan Beulich) v13: - add commit message. (suggested by Jan Beulich) - set 'alt_type' for L2 CAT. (suggested by Jan Beulich) - define a static string array to show which feature's info is printing. (suggested by Jan Beulich) v12: - move 'type[]' assignment into l2_cat_props declaration to make it be 'const'. (suggested by Jan Beulich) - add "L2 CAT" indicator in printk. (suggested by Jan Beulich) - restore mask(0) MSR to default value. (suggested by Jan Beulich) v11: - move l2 cat 'type[]' assignement into 'psr_cpu_init'. - remove COS MSR restore action in 'cpu_init_feature'. - set 'feat_init' to true after CPU init. - modify commit message. v10: - implement L2 CAT case in 'cat_init_feature'. (suggested by Jan Beulich) - changes about 'props'. (suggested by Jan Beulich) - introduce 'PSR_CBM_TYPE_L2'. v9: - modify error handling process in 'psr_cpu_prepare' to reduce redundant codes. - reuse 'cat_init_feature' and 'cat_get_cos_max' for L2 CAT to reduce redundant codes. (suggested by Roger Pau) - remove unnecessary comment. (suggested by Jan Beulich) - move L2 CAT related codes from 'cpu_init_work' into 'psr_cpu_init'. (suggested by Jan Beulich) - do not free resource when allocation fails in 'psr_cpu_prepare'. (suggested by Jan Beulich) v7: - initialize 'l2_cat'. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf'. (suggested by Konrad Rzeszutek Wilk and Jan Beulich) v5: - remove 'feat_l2_cat' free in 'free_feature'. (suggested by Jan Beulich) - encapsulate cpuid registers into 'struct cpuid_leaf_regs'. (suggested by Jan Beulich) - print socket info when 'opt_cpu_info' is true. (suggested by Jan Beulich) - rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'. (suggested by Jan Beulich) - rename 'dat[]' to 'data[]' (suggested by Jan Beulich) - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch because of codes architecture change. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 48 ++++++++++++++++++++++++++++++++++++++--- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 ++ 3 files changed, 48 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index c211c77..320c2c7 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -63,6 +63,7 @@ enum psr_feat_type { FEAT_TYPE_L3_CAT, FEAT_TYPE_L3_CDP, + FEAT_TYPE_L2_CAT, FEAT_TYPE_NUM, FEAT_TYPE_UNKNOWN, }; @@ -159,6 +160,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); * array creation. It is used to transiently store a spare node. */ static struct feat_node *feat_l3; +static struct feat_node *feat_l2_cat; /* Common functions */ #define cat_default_val(len) (0xffffffff >> (32 - (len))) @@ -273,6 +275,12 @@ static int cat_init_feature(const struct cpuid_leaf *regs, struct psr_socket_info *info, enum psr_feat_type type) { + const char * const cat_feat_name[FEAT_TYPE_NUM] = { + "L3 CAT", + "CDP", + "L2 CAT", + }; + /* No valid value so do not enable feature. */ if ( !regs->a || !regs->d ) return -ENOENT; @@ -283,13 +291,17 @@ static int cat_init_feature(const struct cpuid_leaf *regs, switch ( type ) { case FEAT_TYPE_L3_CAT: + case FEAT_TYPE_L2_CAT: if ( feat->cos_max < 1 ) return -ENOENT; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ feat->cos_reg_val[0] = cat_default_val(feat->cbm_len); - wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len)); + wrmsrl((type == FEAT_TYPE_L3_CAT ? + MSR_IA32_PSR_L3_MASK(0) : + MSR_IA32_PSR_L2_MASK(0)), + cat_default_val(feat->cbm_len)); break; @@ -327,8 +339,8 @@ static int cat_init_feature(const struct cpuid_leaf *regs, return 0; printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n", - ((type == FEAT_TYPE_L3_CDP) ? "CDP" : "L3 CAT"), - cpu_to_socket(smp_processor_id()), feat->cos_max, feat->cbm_len); + cat_feat_name[type], cpu_to_socket(smp_processor_id()), + feat->cos_max, feat->cbm_len); return 0; } @@ -389,6 +401,19 @@ static const struct feat_props l3_cdp_props = { .write_msr = l3_cdp_write_msr, }; +/* L2 CAT props */ +static void l2_cat_write_msr(unsigned int cos, uint32_t val, enum cbm_type type) +{ +} + +static const struct feat_props l2_cat_props = { + .cos_num = 1, + .type[0] = PSR_CBM_TYPE_L2, + .alt_type = PSR_CBM_TYPE_UNKNOWN, + .get_feat_info = cat_get_feat_info, + .write_msr = l2_cat_write_msr, +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -1343,6 +1368,10 @@ static int psr_cpu_prepare(void) (feat_l3 = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_l2_cat == NULL && + (feat_l2_cat = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1395,6 +1424,19 @@ static void psr_cpu_init(void) } } + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); + if ( regs.b & PSR_RESOURCE_TYPE_L2 ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s); + + feat = feat_l2_cat; + feat_l2_cat = NULL; + if ( !cat_init_feature(®s, feat, info, FEAT_TYPE_L2_CAT) ) + feat_props[FEAT_TYPE_L2_CAT] = &l2_cat_props; + else + feat_l2_cat = feat; + } + info->feat_init = true; assoc_init: diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 756b23d..4e08de6 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -347,6 +347,7 @@ #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) +#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index 50b8757..18a42f3 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -23,6 +23,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 +#define PSR_RESOURCE_TYPE_L2 0x4 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1 @@ -56,6 +57,7 @@ enum cbm_type { PSR_CBM_TYPE_L3, PSR_CBM_TYPE_L3_CODE, PSR_CBM_TYPE_L3_DATA, + PSR_CBM_TYPE_L2, PSR_CBM_TYPE_UNKNOWN, };