From patchwork Wed Aug 16 11:22:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 9903491 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4AD516038C for ; Wed, 16 Aug 2017 11:24:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E03327CEA for ; Wed, 16 Aug 2017 11:24:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 32C2A28769; Wed, 16 Aug 2017 11:24:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BC5CF27CEA for ; Wed, 16 Aug 2017 11:24:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dhwOw-0006CM-Au; Wed, 16 Aug 2017 11:22:18 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dhwOv-0006Ag-5D for xen-devel@lists.xen.org; Wed, 16 Aug 2017 11:22:17 +0000 Received: from [193.109.254.147] by server-4.bemta-6.messagelabs.com id 68/E8-02962-8EA24995; Wed, 16 Aug 2017 11:22:16 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeJIrShJLcpLzFFi42JxWrrBXveF1pR Ig21L2S2WfFzM4sDocXT3b6YAxijWzLyk/IoE1oyzyzYyFuwQr5jb9pGtgfGeUBcjJ4eEgL/E yw+TWEFsNgF9id0vPjGB2CIC6hKnOy4CxTk4mAX8JA498AUJCwOZc9s3sICEWQRUJboP1oCEe QU8JabOX80CMVFO4vzxn8wgNqeAl8SFPTvAJgoB1dzasY8VwlaTuNZ/iR2iV1Di5MwnYL3MAh ISB1+8YJ7AyDsLSWoWktQCRqZVjBrFqUVlqUW6RoZ6SUWZ6RkluYmZObqGBmZ6uanFxYnpqTm JScV6yfm5mxiBgcMABDsY/ywLOMQoycGkJMq76OykSCG+pPyUyozE4oz4otKc1OJDjDIcHEoS vLWaUyKFBItS01Mr0jJzgCEMk5bg4FES4X0EkuYtLkjMLc5Mh0idYtTleDXh/zcmIZa8/LxUK XFeb5AiAZCijNI8uBGweLrEKCslzMsIdJQQT0FqUW5mCar8K0ZxDkYlYd5NIFN4MvNK4Da9Aj qCCeiIK+2TQI4oSURISTUwHpWy2rR6g2DMj6g7KunzJEWjpd5w6Gyc1Hbo3XSB2T9/TUxujJo 5vbaH8+nMXFPfW3IzAoWTFR7NkJJLDV1dOm9J4YMtrx69XX1Vrvp+qea23jp7xsPLf4sk5NwU utUjwMBaYb5FafcH48j7te62kWLqiovuzl8vffDOR/PX+8rEfHJPvrCcr8RSnJFoqMVcVJwIA OGR1FSiAgAA X-Env-Sender: prvs=3941fdc67=Andrew.Cooper3@citrix.com X-Msg-Ref: server-4.tower-27.messagelabs.com!1502882533!111246128!3 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 5944 invoked from network); 16 Aug 2017 11:22:15 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-4.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 16 Aug 2017 11:22:15 -0000 X-IronPort-AV: E=Sophos;i="5.41,382,1498521600"; d="scan'208";a="443987611" From: Andrew Cooper To: Xen-devel Date: Wed, 16 Aug 2017 12:22:10 +0100 Message-ID: <1502882530-31700-5-git-send-email-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1502882530-31700-1-git-send-email-andrew.cooper3@citrix.com> References: <1502882530-31700-1-git-send-email-andrew.cooper3@citrix.com> MIME-Version: 1.0 Cc: Andrew Cooper , Jan Beulich Subject: [Xen-devel] [PATCH v2 4/4] xen/x86: Correct mandatory and SMP barrier definitions X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Barriers are a complicated topic, a source of confusion, and their incorrect use is a common cause of bugs. It *really* doesn't help when Xen's API is the same as Linux, but its ABI different. Bring the two back in line, so programmers stand a chance of actually getting their usage correct. Drop the links in the comment, both of which are now stale. Instead, refer to the vendor system manuals. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Dario Faggioli Reviewed-by: Jan Beulich --- CC: Jan Beulich v2: * Keep mandatory barrier definitions * Drop stale documentation links --- xen/include/asm-x86/system.h | 28 ++++++++++++++++------------ xen/include/asm-x86/x86_64/system.h | 3 --- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/xen/include/asm-x86/system.h b/xen/include/asm-x86/system.h index 9cb6fd7..3d21291 100644 --- a/xen/include/asm-x86/system.h +++ b/xen/include/asm-x86/system.h @@ -164,23 +164,27 @@ static always_inline unsigned long __xadd( ((typeof(*(ptr)))__xadd(ptr, (typeof(*(ptr)))(v), sizeof(*(ptr)))) /* + * Mandatory barriers, for enforced ordering of reads and writes, e.g. for use + * with MMIO devices mapped with reduced cacheability. + */ +#define mb() asm volatile ("mfence" ::: "memory") +#define rmb() asm volatile ("lfence" ::: "memory") +#define wmb() asm volatile ("sfence" ::: "memory") + +/* + * SMP barriers, for ordering of reads and writes between CPUs, most commonly + * used with shared memory. + * * Both Intel and AMD agree that, from a programmer's viewpoint: * Loads cannot be reordered relative to other loads. * Stores cannot be reordered relative to other stores. - * - * Intel64 Architecture Memory Ordering White Paper - * - * - * AMD64 Architecture Programmer's Manual, Volume 2: System Programming - * + * Loads may be reordered ahead of an unaliasing store. + * + * Refer to the vendor system programming manuals for further details. */ -#define rmb() barrier() -#define wmb() barrier() - #define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() +#define smp_rmb() barrier() +#define smp_wmb() barrier() #define set_mb(var, value) do { xchg(&var, value); } while (0) #define set_wmb(var, value) do { var = value; smp_wmb(); } while (0) diff --git a/xen/include/asm-x86/x86_64/system.h b/xen/include/asm-x86/x86_64/system.h index 88beae1..6b56761 100644 --- a/xen/include/asm-x86/x86_64/system.h +++ b/xen/include/asm-x86/x86_64/system.h @@ -80,7 +80,4 @@ static always_inline __uint128_t __cmpxchg16b( _rc; \ }) -#define mb() \ - asm volatile ( "mfence" : : : "memory" ) - #endif /* __X86_64_SYSTEM_H__ */