From patchwork Fri Sep 22 03:01:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "lan,Tianyu" X-Patchwork-Id: 9965599 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 63E0D600C5 for ; Fri, 22 Sep 2017 09:12:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D68128501 for ; Fri, 22 Sep 2017 09:12:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5229E28517; Fri, 22 Sep 2017 09:12:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DCF0628757 for ; Fri, 22 Sep 2017 09:12:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dvJyU-0004B0-GO; Fri, 22 Sep 2017 09:10:18 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dvJyT-00048n-4V for xen-devel@lists.xen.org; Fri, 22 Sep 2017 09:10:17 +0000 Received: from [193.109.254.147] by server-4.bemta-6.messagelabs.com id 20/F0-03283-873D4C95; Fri, 22 Sep 2017 09:10:16 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRWlGSWpSXmKPExsXS1taRolt++Ui kwa9tVhZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8b3q88ZC85qVzxsd2lgnK7UxcjJISRQKXFo Rgs7iC0hwCtxZNkMVgjbX2LP25nMXYxcQDUdjBJv969jBEmwCahLnFg8EcwWEZCWuPb5MiNIE bPAZiaJuWtmsYAkhAXCJN5c6QGbyiKgKnHh4zawqbwCrhLTNv5hhtigIDHl4XswmxMo/qtvOx PERS4SrUv3M01g5F3AyLCKUaM4tagstUjX2EAvqSgzPaMkNzEzR9fQwEwvN7W4ODE9NScxqVg vOT93EyMwHBiAYAfj37WBhxglOZiURHnfnz8SKcSXlJ9SmZFYnBFfVJqTWnyIUYaDQ0mCt/0S UE6wKDU9tSItMwcYmDBpCQ4eJRHeRJA0b3FBYm5xZjpE6hSjLkfHzbt/mIRY8vLzUqXEefVAi gRAijJK8+BGwKLkEqOslDAvI9BRQjwFqUW5mSWo8q8YxTkYlYR5s0Gm8GTmlcBtegV0BBPQEe WrwY4oSURISTUwFjYycXEU/Zr2LPm1cRf3OrVtMcVhfA5OH1numshwc5mwH5zyWaT4cuHdmY4 KIX6Ltt54tui8zZP2xPnC/XuWuS78YVznOmPvCRctq6V2jZErV/z8J+jyeE/0w+i5IcfPZ99Q Eu6fW9j4oYvrrx5PTuHiQ3uCfphvvFT+8Mi+oz0za+8s030nrsRSnJFoqMVcVJwIAGZE+7WNA gAA X-Env-Sender: tianyu.lan@intel.com X-Msg-Ref: server-9.tower-27.messagelabs.com!1506071413!118094449!1 X-Originating-IP: [134.134.136.100] X-SpamReason: No, hits=1.3 required=7.0 tests=BODY_RANDOM_LONG, DATE_IN_PAST_06_12 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24161 invoked from network); 22 Sep 2017 09:10:15 -0000 Received: from mga07.intel.com (HELO mga07.intel.com) (134.134.136.100) by server-9.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 22 Sep 2017 09:10:15 -0000 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP; 22 Sep 2017 02:10:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,427,1500966000"; d="scan'208";a="154791943" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.141]) by fmsmga006.fm.intel.com with ESMTP; 22 Sep 2017 02:10:10 -0700 From: Lan Tianyu To: xen-devel@lists.xen.org Date: Thu, 21 Sep 2017 23:01:54 -0400 Message-Id: <1506049330-11196-14-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1506049330-11196-1-git-send-email-tianyu.lan@intel.com> References: <1506049330-11196-1-git-send-email-tianyu.lan@intel.com> Cc: Lan Tianyu , kevin.tian@intel.com, sstabellini@kernel.org, wei.liu2@citrix.com, George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, tim@xen.org, jbeulich@suse.com, roger.pau@citrix.com, Chao Gao Subject: [Xen-devel] [PATCH V3 13/29] x86/vvtd: Set Interrupt Remapping Table Pointer through GCMD X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chao Gao Software sets this field to set/update the interrupt remapping table pointer used by hardware. The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address (IRTA_REG) register. This patch emulates this operation and adds some new fields in VVTD to track info (e.g. the table's gfn and max supported entries) of interrupt remapping table. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- v3: - ignore unaligned r/w of vt-d hardware registers and return X86EMUL_OK --- xen/drivers/passthrough/vtd/iommu.h | 12 ++++++- xen/drivers/passthrough/vtd/vvtd.c | 69 +++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index ef038c9..a0d5ec8 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -153,6 +153,8 @@ #define DMA_GCMD_IRE (((u64)1) << 25) #define DMA_GCMD_SIRTP (((u64)1) << 24) #define DMA_GCMD_CFI (((u64)1) << 23) +/* mask of one-shot bits */ +#define DMA_GCMD_ONE_SHOT_MASK 0x96ffffff /* GSTS_REG */ #define DMA_GSTS_TES (((u64)1) << 31) @@ -162,9 +164,17 @@ #define DMA_GSTS_WBFS (((u64)1) << 27) #define DMA_GSTS_QIES (((u64)1) <<26) #define DMA_GSTS_IRES (((u64)1) <<25) -#define DMA_GSTS_SIRTPS (((u64)1) << 24) +#define DMA_GSTS_SIRTPS_SHIFT 24 +#define DMA_GSTS_SIRTPS (((u64)1) << DMA_GSTS_SIRTPS_SHIFT) #define DMA_GSTS_CFIS (((u64)1) <<23) +/* IRTA_REG */ +/* The base of 4KB aligned interrupt remapping table */ +#define DMA_IRTA_ADDR(val) ((val) & ~0xfffULL) +/* The size of remapping table is 2^(x+1), where x is the size field in IRTA */ +#define DMA_IRTA_S(val) (val & 0xf) +#define DMA_IRTA_SIZE(val) (1UL << (DMA_IRTA_S(val) + 1)) + /* PMEN_REG */ #define DMA_PMEN_EPM (((u32)1) << 31) #define DMA_PMEN_PRS (((u32)1) << 0) diff --git a/xen/drivers/passthrough/vtd/vvtd.c b/xen/drivers/passthrough/vtd/vvtd.c index a3002c3..6736956 100644 --- a/xen/drivers/passthrough/vtd/vvtd.c +++ b/xen/drivers/passthrough/vtd/vvtd.c @@ -32,6 +32,13 @@ /* Supported capabilities by vvtd */ unsigned int vvtd_caps = VIOMMU_CAP_IRQ_REMAPPING; +struct hvm_hw_vvtd_status { + uint32_t eim_enabled : 1; + uint32_t irt_max_entry; + /* Interrupt remapping table base gfn */ + uint64_t irt; +}; + union hvm_hw_vvtd_regs { uint32_t data32[256]; uint64_t data64[128]; @@ -43,6 +50,8 @@ struct vvtd { uint64_t length; /* Point back to the owner domain */ struct domain *domain; + + struct hvm_hw_vvtd_status status; union hvm_hw_vvtd_regs *regs; struct page_info *regs_page; }; @@ -70,6 +79,11 @@ struct vvtd *domain_vvtd(struct domain *d) return (d->viommu) ? d->viommu->priv : NULL; } +static inline void vvtd_set_bit(struct vvtd *vvtd, uint32_t reg, int nr) +{ + __set_bit(nr, &vvtd->regs->data32[reg/sizeof(uint32_t)]); +} + static inline void vvtd_set_reg(struct vvtd *vtd, uint32_t reg, uint32_t value) { vtd->regs->data32[reg/sizeof(uint32_t)] = value; @@ -91,6 +105,44 @@ static inline uint64_t vvtd_get_reg_quad(struct vvtd *vtd, uint32_t reg) return vtd->regs->data64[reg/sizeof(uint64_t)]; } +static void vvtd_handle_gcmd_sirtp(struct vvtd *vvtd, uint32_t val) +{ + uint64_t irta = vvtd_get_reg_quad(vvtd, DMAR_IRTA_REG); + + if ( !(val & DMA_GCMD_SIRTP) ) + return; + + vvtd->status.irt = DMA_IRTA_ADDR(irta) >> PAGE_SHIFT; + vvtd->status.irt_max_entry = DMA_IRTA_SIZE(irta); + vvtd->status.eim_enabled = !!(irta & IRTA_EIME); + vvtd_info("Update IR info (addr=%lx eim=%d size=%d).", + vvtd->status.irt, vvtd->status.eim_enabled, + vvtd->status.irt_max_entry); + vvtd_set_bit(vvtd, DMAR_GSTS_REG, DMA_GSTS_SIRTPS_SHIFT); +} + +static int vvtd_write_gcmd(struct vvtd *vvtd, uint32_t val) +{ + uint32_t orig = vvtd_get_reg(vvtd, DMAR_GSTS_REG); + uint32_t changed; + + orig = orig & DMA_GCMD_ONE_SHOT_MASK; /* reset the one-shot bits */ + changed = orig ^ val; + + if ( !changed ) + return X86EMUL_OKAY; + + if ( changed & (changed - 1) ) + vvtd_info("Guest attempts to write %x to GCMD (current GSTS is %x)," + "it would lead to update multiple fields", + val, orig); + + if ( changed & DMA_GCMD_SIRTP ) + vvtd_handle_gcmd_sirtp(vvtd, val); + + return X86EMUL_OKAY; +} + static int vvtd_in_range(struct vcpu *v, unsigned long addr) { struct vvtd *vvtd = domain_vvtd(v->domain); @@ -135,12 +187,17 @@ static int vvtd_write(struct vcpu *v, unsigned long addr, { switch ( offset ) { + case DMAR_GCMD_REG: + return vvtd_write_gcmd(vvtd, val); + case DMAR_IEDATA_REG: case DMAR_IEADDR_REG: case DMAR_IEUADDR_REG: case DMAR_FEDATA_REG: case DMAR_FEADDR_REG: case DMAR_FEUADDR_REG: + case DMAR_IRTA_REG: + case DMAR_IRTA_REG_HI: vvtd_set_reg(vvtd, offset, val); break; @@ -148,6 +205,18 @@ static int vvtd_write(struct vcpu *v, unsigned long addr, break; } } + else /* len == 8 */ + { + switch ( offset ) + { + case DMAR_IRTA_REG: + vvtd_set_reg_quad(vvtd, DMAR_IRTA_REG, val); + break; + + default: + break; + } + } return X86EMUL_OKAY; }