diff mbox

[v8,01/11] arm: traps: use only least 32 bits of fid in PSCI handler

Message ID 1507650771-16631-2-git-send-email-volodymyr_babchuk@epam.com (mailing list archive)
State New, archived
Headers show

Commit Message

Volodymyr Babchuk Oct. 10, 2017, 3:52 p.m. UTC 
According to SMCCC (ARM DEN 0028B, page 12), function id is
stored in least 32 bits of r0/x0 register:

    The least significant 32-bits are used, and the most significant
    32-bits are zero.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Julien Grall <julien.grall@arm.com>
---

* Removed part of the quote from ARM DEN 0028B due to typo.

* This patch needs to be backported

---
xen/arch/arm/traps.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 701fdc8..0cff83e 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1463,14 +1463,14 @@  static void do_debug_trap(struct cpu_user_regs *regs, unsigned int code)
 #endif
 
 /* helper function for checking arm mode 32/64 bit */
-static inline int psci_mode_check(struct domain *d, register_t fid)
+static inline int psci_mode_check(struct domain *d, uint32_t fid)
 {
         return !( is_64bit_domain(d)^( (fid & PSCI_0_2_64BIT) >> 30 ) );
 }
 
 static void do_trap_psci(struct cpu_user_regs *regs)
 {
-    register_t fid = PSCI_ARG(regs,0);
+    uint32_t fid = PSCI_ARG32(regs,0);
 
     /* preloading in case psci_mode_check fails */
     PSCI_RESULT_REG(regs) = PSCI_INVALID_PARAMETERS;