From patchwork Sat Oct 21 20:02:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luwei Kang X-Patchwork-Id: 10021649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3AAF660381 for ; Sun, 22 Oct 2017 09:49:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 256B828700 for ; Sun, 22 Oct 2017 09:49:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A50428775; Sun, 22 Oct 2017 09:49:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.2 required=2.0 tests=BAYES_00, DATE_IN_PAST_12_24, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 78AF928700 for ; Sun, 22 Oct 2017 09:49:08 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e6Cqh-0004Cq-UI; Sun, 22 Oct 2017 09:47:15 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e6Cqg-0004Bv-GJ for xen-devel@lists.xen.org; Sun, 22 Oct 2017 09:47:14 +0000 Received: from [193.109.254.147] by server-3.bemta-6.messagelabs.com id 7A/20-14867-1296CE95; Sun, 22 Oct 2017 09:47:13 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFLMWRWlGSWpSXmKPExsVywNykQlcx802 kwdIN7BZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bC691sBevUKr7N1G5gfCTXxcjFISQwnVFi 89Ee5i5GTg4JAV6JI8tmsELYARKTF80AiwsJlEr0z5jJBGKzCahLbH2/EaxGREBa4trny4wgg 5gFpjJJPNp2AiwhLOAhMW0XxFAWAVWJtdvPgsV5BVwkOpr7oRbISdw81wlWwyngKnHx3hJWiG UuEgfPdzBOYORdwMiwilGjOLWoLLVI18hUL6koMz2jJDcxM0fX0MBMLze1uDgxPTUnMalYLzk /dxMjMBwYgGAH46oFgYcYJTmYlER5K969ihTiS8pPqcxILM6ILyrNSS0+xCjDwaEkwfs1/U2k kGBRanpqRVpmDjAwYdISHDxKIrxXQNK8xQWJucWZ6RCpU4y6HB037/5hEmLJy89LlRLn/Q1SJ ABSlFGaBzcCFiWXGGWlhHkZgY4S4ilILcrNLEGVf8UozsGoJMwrkAE0hSczrwRu0yugI5iAjp C1BzuiJBEhJdXAGH/a8PXR+/YvV9Zk2dxMaXRuNP2fs8Dm8Ltwe1ankugzFnduzObf5LvjQXb rkfht238tC87PaA5MnrVvnvFf4T+J9dZRS22LLxplGf3L+2V4YufTKzsf6MbOTPmf+nvZjCDd pYkHpFl6d//6N/fMnuWLVJvZH0c82tgfOIvPwehCAC8nw6ZcFyWW4oxEQy3mouJEAJyDN3eNA gAA X-Env-Sender: luwei.kang@intel.com X-Msg-Ref: server-2.tower-27.messagelabs.com!1508665620!53255653!4 X-Originating-IP: [192.55.52.120] X-SpamReason: No, hits=1.0 required=7.0 tests=DATE_IN_PAST_12_24 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6762 invoked from network); 22 Oct 2017 09:47:12 -0000 Received: from mga04.intel.com (HELO mga04.intel.com) (192.55.52.120) by server-2.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 22 Oct 2017 09:47:12 -0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Oct 2017 02:47:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.43,416,1503385200"; d="scan'208"; a="1208603537" Received: from vmm.bj.intel.com ([10.238.135.172]) by fmsmga001.fm.intel.com with ESMTP; 22 Oct 2017 02:47:09 -0700 From: Luwei Kang To: xen-devel@lists.xen.org Date: Sun, 22 Oct 2017 04:02:26 +0800 Message-Id: <1508616147-17310-6-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508616147-17310-1-git-send-email-luwei.kang@intel.com> References: <1508616147-17310-1-git-send-email-luwei.kang@intel.com> Cc: kevin.tian@intel.com, sstabellini@kernel.org, wei.liu2@citrix.com, jun.nakajima@intel.com, konrad.wilk@oracle.com, George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, tim@xen.org, jbeulich@suse.com, Luwei Kang Subject: [Xen-devel] [PATCH 5/6] x86: implement intel processor trace context switch X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implement Intel proecessor trace context switch. Signed-off-by: Luwei Kang --- xen/arch/x86/cpu/intel_pt.c | 79 ++++++++++++++++++++++++++++++++++++++ xen/arch/x86/hvm/vmx/vmx.c | 4 ++ xen/include/asm-x86/hvm/vmx/vmcs.h | 2 + xen/include/asm-x86/intel_pt.h | 4 ++ 4 files changed, 89 insertions(+) diff --git a/xen/arch/x86/cpu/intel_pt.c b/xen/arch/x86/cpu/intel_pt.c index be06d55..411b922 100644 --- a/xen/arch/x86/cpu/intel_pt.c +++ b/xen/arch/x86/cpu/intel_pt.c @@ -21,7 +21,86 @@ #include #include #include +#include +#include /* intel_pt: Flag to enable Intel Processor Trace (default on). */ bool_t __read_mostly opt_intel_pt = 1; boolean_param("intel_pt", opt_intel_pt); + +static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_num) +{ + u32 i; + wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); + wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); + wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK_PTRS, ctx->output_mask_ptrs); + wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); + for ( i = 0; i < addr_num; i++ ) + wrmsrl(MSR_IA32_RTIT_ADDR0_A + i, ctx->addr[i]); +} + +static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_num) +{ + u32 i; + rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); + rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); + rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK_PTRS, ctx->output_mask_ptrs); + rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); + for ( i = 0; i < addr_num; i++ ) + rdmsrl(MSR_IA32_RTIT_ADDR0_A + i, ctx->addr[i]); +} + +void pt_guest_enter(struct vcpu *v) +{ + struct pt_desc *pt = &v->arch.hvm_vmx.pt_desc; + + if ( pt->intel_pt_enabled ) + { + vmx_vmcs_enter(v); + __vmwrite(GUEST_IA32_RTIT_CTL, pt->guest_pt_ctx.ctl); + vmx_vmcs_exit(v); + + pt_load_msr(&pt->guest_pt_ctx, pt->addr_num); + } +} + +void pt_guest_exit(struct vcpu *v) +{ + struct pt_desc *pt = &v->arch.hvm_vmx.pt_desc; + + if ( pt->intel_pt_enabled ) + { + vmx_vmcs_enter(v); + __vmread(GUEST_IA32_RTIT_CTL, &pt->guest_pt_ctx.ctl); + vmx_vmcs_exit(v); + + pt_save_msr(&pt->guest_pt_ctx, pt->addr_num); + } +} + +void pt_vcpu_init(struct vcpu *v) +{ + struct pt_desc *pt = &v->arch.hvm_vmx.pt_desc; + unsigned int eax, ebx, ecx, edx; + + memset(pt, 0, sizeof(struct pt_desc)); + pt->intel_pt_enabled = false; + + if ( !cpu_has_intel_pt || !opt_intel_pt || + !(v->arch.hvm_vmx.secondary_exec_control & SECONDARY_EXEC_PT_USE_GPA) ) + return; + + /* get the number of address ranges */ + if ( cpuid_eax(0x14) == 1 ) + cpuid_count(0x14, 1, &eax, &ebx, &ecx, &edx); + else + return; + + pt->addr_num = eax & 0x7; + pt->guest_pt_ctx.output_mask_ptrs = 0x7F; + pt->intel_pt_enabled = true; + + vmx_vmcs_enter(v); + __vmwrite(GUEST_IA32_RTIT_CTL, 0); + vmx_vmcs_exit(v); +} diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index a5c2bd7..ea23dbd 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -468,6 +468,8 @@ static int vmx_vcpu_initialise(struct vcpu *v) if ( v->vcpu_id == 0 ) v->arch.user_regs.rax = 1; + pt_vcpu_init(v); + return 0; } @@ -3492,6 +3494,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) __vmread(GUEST_RSP, ®s->rsp); __vmread(GUEST_RFLAGS, ®s->rflags); + pt_guest_exit(v); hvm_invalidate_regs_fields(regs); if ( paging_mode_hap(v->domain) ) @@ -4260,6 +4263,7 @@ bool vmx_vmenter_helper(const struct cpu_user_regs *regs) } } + pt_guest_enter(curr); out: if ( unlikely(curr->arch.hvm_vmx.lbr_fixup_enabled) ) lbr_fixup(); diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index 33ec3e6..46c386f 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -421,6 +421,8 @@ enum vmcs_field { GUEST_PDPTE0 = 0x0000280a, #define GUEST_PDPTE(n) (GUEST_PDPTE0 + (n) * 2) /* n = 0...3 */ GUEST_BNDCFGS = 0x00002812, + GUEST_IA32_RTIT_CTL = 0x00002814, + GUEST_IA32_RTIT_CTL_HIGH = 0x00002815, HOST_PAT = 0x00002c00, HOST_EFER = 0x00002c02, HOST_PERF_GLOBAL_CTRL = 0x00002c04, diff --git a/xen/include/asm-x86/intel_pt.h b/xen/include/asm-x86/intel_pt.h index 78e3a37..29ea466 100644 --- a/xen/include/asm-x86/intel_pt.h +++ b/xen/include/asm-x86/intel_pt.h @@ -40,4 +40,8 @@ struct pt_desc { extern bool_t opt_intel_pt; +void pt_vcpu_init(struct vcpu *v); +void pt_guest_enter(struct vcpu *v); +void pt_guest_exit(struct vcpu *v); + #endif /* __ASM_X86_HVM_INTEL_PT_H_ */