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[6/6] x86: Pass through intel processor trace MSRs

Message ID 1508616147-17310-7-git-send-email-luwei.kang@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Luwei Kang Oct. 21, 2017, 8:02 p.m. UTC 
This patch pass through Intel processor trace MSRs
to guest.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 xen/arch/x86/cpu/intel_pt.c | 8 ++++++++
 1 file changed, 8 insertions(+)
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Patch

diff --git a/xen/arch/x86/cpu/intel_pt.c b/xen/arch/x86/cpu/intel_pt.c
index 411b922..8e83b87 100644
--- a/xen/arch/x86/cpu/intel_pt.c
+++ b/xen/arch/x86/cpu/intel_pt.c
@@ -82,6 +82,7 @@  void pt_vcpu_init(struct vcpu *v)
 {
     struct pt_desc *pt = &v->arch.hvm_vmx.pt_desc;
     unsigned int eax, ebx, ecx, edx;
+    int i;
 
     memset(pt, 0, sizeof(struct pt_desc));
     pt->intel_pt_enabled = false;
@@ -102,5 +103,12 @@  void pt_vcpu_init(struct vcpu *v)
 
     vmx_vmcs_enter(v);
     __vmwrite(GUEST_IA32_RTIT_CTL, 0);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_CTL, VMX_MSR_RW);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_STATUS, VMX_MSR_RW);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_OUTPUT_BASE, VMX_MSR_RW);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_OUTPUT_MASK_PTRS, VMX_MSR_RW);
+    vmx_clear_msr_intercept(v, MSR_IA32_RTIT_CR3_MATCH, VMX_MSR_RW);
+    for ( i = 0; i < pt->addr_num; i++ )
+        vmx_clear_msr_intercept(v, MSR_IA32_RTIT_ADDR0_A + i, VMX_MSR_RW);
     vmx_vmcs_exit(v);
 }