From patchwork Fri Nov 17 06:22:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Gao X-Patchwork-Id: 10062341 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1AD0A6023A for ; Fri, 17 Nov 2017 06:27:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0CC742A539 for ; Fri, 17 Nov 2017 06:27:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 01ABD2A990; Fri, 17 Nov 2017 06:27:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4D1E52A825 for ; Fri, 17 Nov 2017 06:27:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eFa5L-0000kr-F4; Fri, 17 Nov 2017 06:25:07 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eFa5J-0000j6-PD for xen-devel@lists.xen.org; Fri, 17 Nov 2017 06:25:05 +0000 Received: from [85.158.143.35] (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256 bits)) by server-2.bemta-6.messagelabs.com id 23/E5-05188-1C08E0A5; Fri, 17 Nov 2017 06:25:05 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRWlGSWpSXmKPExsVywNwkVvdAA1+ UwYZeeYslHxezODB6HN39mymAMYo1My8pvyKBNePC8amsBbsDKjadfsbSwPjeuouRi0NIYDqj xJQNK1m7GDk5JAR4JY4smwFlB0ic2XeJCcQWEqiSuLduCVicTUBZ4uLXXjYQW0RAWuLa58uMI IOYBZ4zSyxZ95cRJCEs4C6xae0lli5GDg4WAVWJBVPAwrwCzhKTHi9ggZivIDHl4XtmEJsTKL 7/zUGoXU4SB9dNY5rAyLuAkWEVo3pxalFZapGupV5SUWZ6RkluYmaOrqGBmV5uanFxYnpqTmJ SsV5yfu4mRmAwMADBDsa7mwIOMUpyMCmJ8vKY80UJ8SXlp1RmJBZnxBeV5qQWH2KU4eBQkuD1 qgfKCRalpqdWpGXmAMMSJi3BwaMkwlsAkuYtLkjMLc5Mh0idYjTmeDbzdQMzx7SrrU3MQix5+ XmpUuK8xSClAiClGaV5cINg8XKJUVZKmJcR6DQhnoLUotzMElT5V4ziHIxKwryVIFN4MvNK4P a9AjqFCegUmxvcIKeUJCKkpBoYQ1amPXFX38xVob/4wBrBlZOnPo1r37qyeroVZ+vGql1aId+ crhdrGh3veNWRw9Z6+8qH8JTuvIpK5qXNL5gdH3xjXyEQe+t46Zv90xjkMrbF3372Tu68SKRz jUtjo8GLKWfYTd1n2y06yBMq8/ddz5aiuY95+X83+eb96QxkqHD93CnOGBGtxFKckWioxVxUn AgAXpcsf5ICAAA= X-Env-Sender: chao.gao@intel.com X-Msg-Ref: server-12.tower-21.messagelabs.com!1510899867!82378134!12 X-Originating-IP: [192.55.52.93] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTkyLjU1LjUyLjkzID0+IDMyNDY2NQ==\n X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 57785 invoked from network); 17 Nov 2017 06:25:03 -0000 Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by server-12.tower-21.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Nov 2017 06:25:03 -0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Nov 2017 22:25:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.44,407,1505804400"; d="scan'208"; a="1245165119" Received: from skl-4s-chao.sh.intel.com ([10.239.48.9]) by fmsmga002.fm.intel.com with ESMTP; 16 Nov 2017 22:25:00 -0800 From: Chao Gao To: xen-devel@lists.xen.org Date: Fri, 17 Nov 2017 14:22:18 +0800 Message-Id: <1510899755-40237-12-git-send-email-chao.gao@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1510899755-40237-1-git-send-email-chao.gao@intel.com> References: <1510899755-40237-1-git-send-email-chao.gao@intel.com> Cc: Lan Tianyu , Kevin Tian , Stefano Stabellini , Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Ian Jackson , Tim Deegan , Jan Beulich , Andrew Cooper , Chao Gao , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [Xen-devel] [PATCH v4 11/28] x86/vvtd: Process interrupt remapping request X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP When a remapping interrupt request arrives, remapping hardware computes the interrupt_index per the algorithm described in VTD spec "Interrupt Remapping Table", interprets the IRTE and generates a remapped interrupt request. This patch introduces viommu_handle_irq_request() to emulate the process how remapping hardware handles a remapping interrupt request. This patch also introduces a counter inflight_intr, which is used to count the number of interrupt are being handled. The reason why we should have this counter is VT-d hardware should drain in-flight interrups before setting flags to show that some operations are completed. These operations include enabling interrupt remapping and performing a kind of invalidation requests. In vvtd, we also try to drain in-flight interrupts by waiting the inflight_intr is decreased to 0. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu --- v4: - use "#define" to define interrupt remapping transition faults rather than using an enum - use switch-case rather than if-else in irq_remapping_request_index() and vvtd_irq_request_sanity_check() - introduce a counter inflight_intr v3: - Encode map_guest_page()'s error into void* to avoid using another parameter --- xen/drivers/passthrough/vtd/iommu.h | 15 +++ xen/drivers/passthrough/vtd/vvtd.c | 219 ++++++++++++++++++++++++++++++++++++ 2 files changed, 234 insertions(+) diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index 9c59aeb..82edd2a 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -216,6 +216,15 @@ #define dma_frcd_source_id(c) (c & 0xffff) #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */ +/* Interrupt remapping transition faults */ +#define VTD_FR_IR_REQ_RSVD 0x20 +#define VTD_FR_IR_INDEX_OVER 0x21 +#define VTD_FR_IR_ENTRY_P 0x22 +#define VTD_FR_IR_ROOT_INVAL 0x23 +#define VTD_FR_IR_IRTE_RSVD 0x24 +#define VTD_FR_IR_REQ_COMPAT 0x25 +#define VTD_FR_IR_SID_ERR 0x26 + /* * 0: Present * 1-11: Reserved @@ -356,6 +365,12 @@ struct iremap_entry { }; /* + * When VT-d doesn't enable extended interrupt mode, hardware interprets + * 8-bits ([15:8]) of Destination-ID field in the IRTEs. + */ +#define IRTE_xAPIC_DEST_MASK 0xff00 + +/* * Posted-interrupt descriptor address is 64 bits with 64-byte aligned, only * the upper 26 bits of lest significiant 32 bits is available. */ diff --git a/xen/drivers/passthrough/vtd/vvtd.c b/xen/drivers/passthrough/vtd/vvtd.c index 06e522a..927e715 100644 --- a/xen/drivers/passthrough/vtd/vvtd.c +++ b/xen/drivers/passthrough/vtd/vvtd.c @@ -22,11 +22,15 @@ #include #include #include +#include #include +#include +#include #include #include #include "iommu.h" +#include "vtd.h" /* Supported capabilities by vvtd */ #define VVTD_MAX_CAPS VIOMMU_CAP_IRQ_REMAPPING @@ -52,6 +56,8 @@ struct vvtd { uint64_t base_addr; /* Point back to the owner domain */ struct domain *domain; + /* # of in-flight interrupts */ + atomic_t inflight_intr; struct hvm_hw_vvtd hw; void *irt_base; @@ -181,6 +187,109 @@ static void unmap_guest_pages(void *va, uint32_t nr) put_page_and_type(mfn_to_page(mfn[i])); } +static int vvtd_delivery(struct domain *d, uint8_t vector, + uint32_t dest, bool dest_mode, + uint8_t delivery_mode, uint8_t trig_mode) +{ + struct vlapic *target; + struct vcpu *v; + + switch ( delivery_mode ) + { + case dest_LowestPrio: + target = vlapic_lowest_prio(d, NULL, 0, dest, dest_mode); + if ( target != NULL ) + { + vvtd_debug("d%d: dest=v%d dlm=%x vector=%d trig_mode=%d\n", + vlapic_domain(target)->domain_id, + vlapic_vcpu(target)->vcpu_id, + delivery_mode, vector, trig_mode); + vlapic_set_irq(target, vector, trig_mode); + break; + } + vvtd_debug("d%d: null round robin: vector=%02x\n", + d->domain_id, vector); + break; + + case dest_Fixed: + for_each_vcpu ( d, v ) + if ( vlapic_match_dest(vcpu_vlapic(v), NULL, 0, dest, dest_mode) ) + { + vvtd_debug("d%d: dest=v%d dlm=%x vector=%d trig_mode=%d\n", + v->domain->domain_id, v->vcpu_id, + delivery_mode, vector, trig_mode); + vlapic_set_irq(vcpu_vlapic(v), vector, trig_mode); + } + break; + + case dest_NMI: + for_each_vcpu ( d, v ) + if ( vlapic_match_dest(vcpu_vlapic(v), NULL, 0, dest, dest_mode) && + !test_and_set_bool(v->nmi_pending) ) + vcpu_kick(v); + break; + + default: + gdprintk(XENLOG_WARNING, "Unsupported VTD delivery mode %d\n", + delivery_mode); + return -EINVAL; + } + + return 0; +} + +/* Computing the IRTE index for a given interrupt request. When success, return + * 0 and set index to reference the corresponding IRTE. Otherwise, return < 0, + * i.e. -1 when the irq request isn't an remapping format. + */ +static int irq_remapping_request_index( + const struct arch_irq_remapping_request *irq, uint32_t *index) +{ + switch ( irq->type ) + { + case VIOMMU_REQUEST_IRQ_MSI: + { + struct msi_msg_remap_entry msi_msg = + { + .address_lo = { .val = irq->msg.msi.addr }, + .data = irq->msg.msi.data, + }; + + if ( !msi_msg.address_lo.format ) + return -1; + + *index = (msi_msg.address_lo.index_15 << 15) + + msi_msg.address_lo.index_0_14; + if ( msi_msg.address_lo.SHV ) + *index += (uint16_t)msi_msg.data; + break; + } + + case VIOMMU_REQUEST_IRQ_APIC: + { + struct IO_APIC_route_remap_entry remap_rte = { .val = irq->msg.rte }; + + if ( !remap_rte.format ) + return -1; + + *index = (remap_rte.index_15 << 15) + remap_rte.index_0_14; + break; + } + + default: + ASSERT_UNREACHABLE(); + } + + return 0; +} + +static inline uint32_t irte_dest(struct vvtd *vvtd, uint32_t dest) +{ + /* In xAPIC mode, only 8-bits([15:8]) are valid */ + return vvtd->hw.eim_enabled ? dest + : MASK_EXTR(dest, IRTE_xAPIC_DEST_MASK); +} + static void write_gcmd_ire(struct vvtd *vvtd, uint32_t val) { bool set = val & DMA_GCMD_IRE; @@ -323,6 +432,115 @@ static const struct hvm_mmio_ops vvtd_mmio_ops = { .write = vvtd_write }; +static void vvtd_handle_fault(struct vvtd *vvtd, + const struct arch_irq_remapping_request *irq, + struct iremap_entry *irte, + unsigned int fault) +{ + switch ( fault ) + { + case VTD_FR_IR_SID_ERR: + case VTD_FR_IR_IRTE_RSVD: + case VTD_FR_IR_ENTRY_P: + if ( qinval_fault_disable(*irte) ) + break; + /* fall through */ + case VTD_FR_IR_REQ_RSVD: + case VTD_FR_IR_INDEX_OVER: + case VTD_FR_IR_ROOT_INVAL: + /* TODO: handle fault (e.g. record and report this fault to VM */ + break; + + default: + vvtd_debug("d%d can't handle VT-d fault %x\n", vvtd->domain->domain_id, + fault); + } + return; +} + +static bool vvtd_irq_request_sanity_check(const struct vvtd *vvtd, + const struct arch_irq_remapping_request *irq) +{ + switch ( irq->type ) + { + case VIOMMU_REQUEST_IRQ_APIC: + { + struct IO_APIC_route_remap_entry rte = { .val = irq->msg.rte }; + + return !rte.reserved; + } + + case VIOMMU_REQUEST_IRQ_MSI: + return true; + } + + ASSERT_UNREACHABLE(); + return false; +} + +static int vvtd_get_entry(struct vvtd *vvtd, + const struct arch_irq_remapping_request *irq, + struct iremap_entry *dest) +{ + uint32_t entry; + struct iremap_entry irte; + int ret = irq_remapping_request_index(irq, &entry); + + ASSERT(!ret); + + vvtd_debug("d%d: interpret a request with index %x\n", + vvtd->domain->domain_id, entry); + + if ( !vvtd_irq_request_sanity_check(vvtd, irq) ) + return VTD_FR_IR_REQ_RSVD; + else if ( entry > vvtd->hw.irt_max_entry ) + return VTD_FR_IR_INDEX_OVER; + else if ( !vvtd->irt_base ) + return VTD_FR_IR_ROOT_INVAL; + + irte = ((struct iremap_entry*)vvtd->irt_base)[entry]; + + if ( !qinval_present(irte) ) + ret = VTD_FR_IR_ENTRY_P; + else if ( (irte.remap.res_1 || irte.remap.res_2 || irte.remap.res_3 || + irte.remap.res_4) ) + ret = VTD_FR_IR_IRTE_RSVD; + + /* FIXME: We don't check against the source ID */ + + dest->val = irte.val; + + return ret; +} + +static int vvtd_handle_irq_request(const struct domain *d, + const struct arch_irq_remapping_request *irq) +{ + struct iremap_entry irte; + int ret; + struct vvtd *vvtd = domain_vvtd(d); + + if ( !vvtd || !vvtd->hw.intremap_enabled ) + return -ENODEV; + + atomic_inc(&vvtd->inflight_intr); + ret = vvtd_get_entry(vvtd, irq, &irte); + if ( ret ) + { + vvtd_handle_fault(vvtd, irq, &irte, ret); + goto out; + } + + ret = vvtd_delivery(vvtd->domain, irte.remap.vector, + irte_dest(vvtd, irte.remap.dst), + irte.remap.dm, irte.remap.dlm, + irte.remap.tm); + + out: + atomic_dec(&vvtd->inflight_intr); + return ret; +} + static void vvtd_reset(struct vvtd *vvtd) { uint64_t cap = cap_set_num_fault_regs(VVTD_FRCD_NUM) @@ -384,6 +602,7 @@ static int vvtd_destroy(struct viommu *viommu) static const struct viommu_ops vvtd_hvm_vmx_ops = { .create = vvtd_create, .destroy = vvtd_destroy, + .handle_irq_request = vvtd_handle_irq_request, }; REGISTER_VIOMMU(vvtd_hvm_vmx_ops);