From patchwork Fri Jul 26 10:37:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrii Anisov X-Patchwork-Id: 11060767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE9F414DB for ; Fri, 26 Jul 2019 10:39:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DFA6928A85 for ; Fri, 26 Jul 2019 10:39:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D3F0D28A8F; Fri, 26 Jul 2019 10:39:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5CAC628A85 for ; Fri, 26 Jul 2019 10:39:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hqxbn-0006ah-Cs; Fri, 26 Jul 2019 10:37:55 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hqxbm-0006ZY-GS for xen-devel@lists.xenproject.org; Fri, 26 Jul 2019 10:37:54 +0000 X-Inumbo-ID: 6b8763af-af91-11e9-8980-bc764e045a96 Received: from mail-lf1-x143.google.com (unknown [2a00:1450:4864:20::143]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 6b8763af-af91-11e9-8980-bc764e045a96; Fri, 26 Jul 2019 10:37:52 +0000 (UTC) Received: by mail-lf1-x143.google.com with SMTP id p197so36726567lfa.2 for ; Fri, 26 Jul 2019 03:37:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nPUZNsAM40LxOGsx6lmuVJn2v89gou977qScNyinde8=; b=oH3E58kh7WZ0HMOZyAUN7LoTmej479AMQMJwg/6jtz4Q/mQZ/t6vl6mwWWzrDUpely PXl33//8uQ213KGj3BYb3Q26xNXEbdyEeMTf/6NGj/7NwbWD+6VO2ZtGnNmHd0AGqHon Dwc0RUXN1CabsMcfEce1XcMYdQfH1QOyRzqDubFP2865wXuXL3awnAbOJ4vLpQnJrI4I qiKYD1rJfc+cnoghJ5Tlc34A7T43rzCV9mMBqI+NkH7xr5q5FqXAJ6wEcgHjGsDP64+O Jn1xTG7Lnmk2xku3laHMT+pFfTQ9uzU+7rOsgfGwXcflHDhNTClC2GfyCfGZCYV8EBek ODzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nPUZNsAM40LxOGsx6lmuVJn2v89gou977qScNyinde8=; b=EH/wfSnX40vO7/KPkuiZAfJEI+x74TGOV0fmwjh9J6U6MNPMkB36UbFyVW+jfouwov MNO4RjTbQ+52J4L2LfFieih2QuykKsjRCoqiRa1l3/swWW7Lh9rhARuHED0breGLww1+ o85vo9Dbq3UsPrzQ2eWURzofkgta6872RCdIEsCv/220WnW9F2VbRV/XMRbEXbksJcxJ 72Cfy8++bUJ1fha73Z5RykalGFdXY8zIrHlMOPkkHpDz7RJSQ/rsdCQiAqpCHz5d7frF TVEmNbLB5I3Dj2zsN1rfVKUkyqudZl9V2Nlo6Vbf9IVrw4a2STtrm645JY0RpzSrpmmQ syiA== X-Gm-Message-State: APjAAAX+PiObgAlGAX4gjweDMH0LNAFGebWuSzP5WVeWtOJ8JWsVAE92 sK4gUDHdYJinjCKwPSCaDD59QdjN X-Google-Smtp-Source: APXvYqzJKw9mi4WrVdzqtUIw/sAMf+Y09Za9RWs5NYRc2SFwkbJ6ZoAs/6S2r0HrRkLtil10LeEbUQ== X-Received: by 2002:ac2:51ab:: with SMTP id f11mr4889140lfk.55.1564137471150; Fri, 26 Jul 2019 03:37:51 -0700 (PDT) Received: from aanisov-work.kyiv.epam.com (ll-22.209.223.85.sovam.net.ua. [85.223.209.22]) by smtp.gmail.com with ESMTPSA id m4sm9938274ljc.56.2019.07.26.03.37.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Jul 2019 03:37:50 -0700 (PDT) From: Andrii Anisov To: xen-devel@lists.xenproject.org Date: Fri, 26 Jul 2019 13:37:39 +0300 Message-Id: <1564137460-25629-7-git-send-email-andrii.anisov@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1564137460-25629-1-git-send-email-andrii.anisov@gmail.com> References: <1564137460-25629-1-git-send-email-andrii.anisov@gmail.com> Subject: [Xen-devel] [RFC 5/6] arm64: call enter_hypervisor_head only when it is needed X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Andrii Anisov On ARM64 we know exactly if trap happened from hypervisor or guest, so we do not need to take that decision. This reduces a condition for all enter_hypervisor_head calls and the function call for traps from the hypervisor mode. Currently, it is implemented for ARM64 only. Integrating the stuff with ARM32 requires moving ` if ( guest_mode(regs) )` condition into ARM32 specific traps.c Signed-off-by: Andrii Anisov --- xen/arch/arm/arm64/entry.S | 6 ++-- xen/arch/arm/traps.c | 75 ++++++++++++++++++++++++---------------------- 2 files changed, 43 insertions(+), 38 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 8f28789..21c710d 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -211,7 +211,7 @@ hyp_irq: entry hyp=1 msr daifclr, #4 mov x0, sp - bl do_trap_irq + bl do_trap_hyp_irq exit hyp=1 guest_sync: @@ -321,7 +321,7 @@ guest_irq: SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT) msr daifclr, #4 mov x0, sp - bl do_trap_irq + bl do_trap_guest_irq 1: exit hyp=0, compat=0 @@ -364,7 +364,7 @@ guest_irq_compat: SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT) msr daifclr, #4 mov x0, sp - bl do_trap_irq + bl do_trap_guest_irq 1: exit hyp=0, compat=1 diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 5a9dc66..13726db 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2011,48 +2011,45 @@ static inline bool needs_ssbd_flip(struct vcpu *v) cpu_require_ssbd_mitigation(); } -static void enter_hypervisor_head(struct cpu_user_regs *regs) +static void enter_hypervisor_head(void) { - if ( guest_mode(regs) ) - { - struct vcpu *v = current; + struct vcpu *v = current; - ASSERT(!local_irq_is_enabled()); + ASSERT(!local_irq_is_enabled()); - /* If the guest has disabled the workaround, bring it back on. */ - if ( needs_ssbd_flip(v) ) - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); + /* If the guest has disabled the workaround, bring it back on. */ + if ( needs_ssbd_flip(v) ) + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); - /* - * If we pended a virtual abort, preserve it until it gets cleared. - * See ARM ARM DDI 0487A.j D1.14.3 (Virtual Interrupts) for details, - * but the crucial bit is "On taking a vSError interrupt, HCR_EL2.VSE - * (alias of HCR.VA) is cleared to 0." - */ - if ( v->arch.hcr_el2 & HCR_VA ) - v->arch.hcr_el2 = READ_SYSREG(HCR_EL2); + /* + * If we pended a virtual abort, preserve it until it gets cleared. + * See ARM ARM DDI 0487A.j D1.14.3 (Virtual Interrupts) for details, + * but the crucial bit is "On taking a vSError interrupt, HCR_EL2.VSE + * (alias of HCR.VA) is cleared to 0." + */ + if ( v->arch.hcr_el2 & HCR_VA ) + v->arch.hcr_el2 = READ_SYSREG(HCR_EL2); #ifdef CONFIG_NEW_VGIC - /* - * We need to update the state of our emulated devices using level - * triggered interrupts before syncing back the VGIC state. - * - * TODO: Investigate whether this is necessary to do on every - * trap and how it can be optimised. - */ - vtimer_update_irqs(v); - vcpu_update_evtchn_irq(v); + /* + * We need to update the state of our emulated devices using level + * triggered interrupts before syncing back the VGIC state. + * + * TODO: Investigate whether this is necessary to do on every + * trap and how it can be optimised. + */ + vtimer_update_irqs(v); + vcpu_update_evtchn_irq(v); #endif - vgic_sync_from_lrs(v); - } + vgic_sync_from_lrs(v); } void do_trap_guest_sync(struct cpu_user_regs *regs) { const union hsr hsr = { .bits = regs->hsr }; - enter_hypervisor_head(regs); + enter_hypervisor_head(); local_irq_enable(); switch ( hsr.ec ) @@ -2188,7 +2185,6 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs) { const union hsr hsr = { .bits = regs->hsr }; - enter_hypervisor_head(regs); local_irq_enable(); switch ( hsr.ec ) @@ -2227,7 +2223,6 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs) void do_trap_hyp_serror(struct cpu_user_regs *regs) { - enter_hypervisor_head(regs); local_irq_enable(); __do_trap_serror(regs, VABORT_GEN_BY_GUEST(regs)); @@ -2235,21 +2230,31 @@ void do_trap_hyp_serror(struct cpu_user_regs *regs) void do_trap_guest_serror(struct cpu_user_regs *regs) { - enter_hypervisor_head(regs); + enter_hypervisor_head(); local_irq_enable(); __do_trap_serror(regs, true); } -void do_trap_irq(struct cpu_user_regs *regs) +void do_trap_guest_irq(struct cpu_user_regs *regs) +{ + enter_hypervisor_head(); + gic_interrupt(regs, 0); +} + +void do_trap_guest_fiq(struct cpu_user_regs *regs) +{ + enter_hypervisor_head(); + gic_interrupt(regs, 1); +} + +void do_trap_hyp_irq(struct cpu_user_regs *regs) { - enter_hypervisor_head(regs); gic_interrupt(regs, 0); } -void do_trap_fiq(struct cpu_user_regs *regs) +void do_trap_hyp_fiq(struct cpu_user_regs *regs) { - enter_hypervisor_head(regs); gic_interrupt(regs, 1); }