@@ -2386,6 +2386,11 @@ libxl_device_pci *libxl_device_pci_list(libxl_ctx *ctx, uint32_t domid,
int *num);
void libxl_device_pci_list_free(libxl_device_pci* list, int num);
+/* FPGA device add. */
+int libxl_add_fpga_node(libxl_ctx *ctx, void *pfdt, int pfdt_size);
+/* FPGA device remove. */
+int libxl_del_fpga_node(libxl_ctx *ctx, char *full_dt_node_path);
+
/*
* Turns the current process into a backend device service daemon
* for a driver domain.
@@ -115,6 +115,7 @@ SRCS-y += libxl_genid.c
SRCS-y += _libxl_types.c
SRCS-y += libxl_flask.c
SRCS-y += _libxl_types_internal.c
+SRCS-y += libxl_fpga.o
ifeq ($(CONFIG_LIBNL),y)
CFLAGS_LIBXL += $(LIBNL3_CFLAGS)
new file mode 100644
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2021 Xilinx Inc.
+ * Author Vikram Garhwal <fnu.vikram@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 only. with the special
+ * exception on linking described in file LICENSE.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ */
+
+#include "libxl_osdeps.h" /* must come before any other headers */
+#include "libxl_internal.h"
+#include <libfdt.h>
+#include <xenguest.h>
+#include <xenctrl.h>
+
+static int check_partial_fdt(libxl__gc *gc, void *fdt, size_t size)
+{
+ int r;
+
+ if (fdt_magic(fdt) != FDT_MAGIC) {
+ LOG(ERROR, "Partial FDT is not a valid Flat Device Tree");
+ return ERROR_FAIL;
+ }
+
+ r = fdt_check_header(fdt);
+ if (r) {
+ LOG(ERROR, "Failed to check the partial FDT (%d)", r);
+ return ERROR_FAIL;
+ }
+
+ if (fdt_totalsize(fdt) > size) {
+ LOG(ERROR, "Partial FDT totalsize is too big");
+ return ERROR_FAIL;
+ }
+
+ return 0;
+}
+
+int libxl_add_fpga_node(libxl_ctx *ctx, void *pfdt, int pfdt_size)
+{
+ int rc = 0;
+ GC_INIT(ctx);
+
+ if (check_partial_fdt(gc, pfdt, pfdt_size)) {
+ LOG(ERROR, "Partial DTB check failed\n");
+ return ERROR_FAIL;
+ } else
+ LOG(DEBUG, "Partial DTB check passed\n");
+
+ /* We don't need to do xc_interface_open here. */
+ rc = xc_domain_add_fpga(ctx->xch, pfdt, pfdt_size);
+
+ if (rc)
+ LOG(ERROR, "%s: Adding partial dtb failed.\n", __func__);
+
+ return rc;
+}
+
+int libxl_del_fpga_node(libxl_ctx *ctx, char *device_path)
+{
+ int rc = 0;
+
+ /* We don't need to do xc_interface_open here. */
+ rc = xc_domain_del_fpga(ctx->xch, device_path);
+
+ return rc;
+}
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> --- tools/include/libxl.h | 5 +++ tools/libs/light/Makefile | 1 + tools/libs/light/libxl_fpga.c | 73 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 tools/libs/light/libxl_fpga.c