diff mbox series

[06/10] iommu/ipmmu-vmsa: Add utlb_offset_base

Message ID 1638035505-16931-7-git-send-email-olekstysh@gmail.com (mailing list archive)
State Superseded
Headers show
Series Add support for Renesas R-Car S4 IPMMU and other misc changes | expand

Commit Message

Oleksandr Tyshchenko Nov. 27, 2021, 5:51 p.m. UTC 
From: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>

This is a non-verbatim port of corresponding Linux upsteam commit:
1289f7f15001c7ed36be6d23cb145c1d5feacdc8

Original commit message:
 commit 1289f7f15001c7ed36be6d23cb145c1d5feacdc8
 Author: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
 Date:   Wed Nov 6 11:35:50 2019 +0900

  iommu/ipmmu-vmsa: Add utlb_offset_base

  Since we will have changed memory mapping of the IPMMU in the future,
  this patch adds a utlb_offset_base into struct ipmmu_features
  for IMUCTR and IMUASID registers. No behavior change.

  Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
  Signed-off-by: Joerg Roedel <jroedel@suse.de>

**********

This is a prereq work needed to add support for S4 series easily
in the future.

Almost the same change as original commit makes, but without updating
struct ipmmu_features_default which Xen driver doesn't have (there is
no support of old Arm32 based Gen2 SoCs).

No change in behavior.

Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
---
 xen/drivers/passthrough/arm/ipmmu-vmsa.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Yoshihiro Shimoda Dec. 14, 2021, 12:07 p.m. UTC | #1 
Hello Oleksandr-san,

> From: Oleksandr Tyshchenko, Sent: Sunday, November 28, 2021 2:52 AM
> 
> From: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
> 
> This is a non-verbatim port of corresponding Linux upsteam commit:
> 1289f7f15001c7ed36be6d23cb145c1d5feacdc8
> 
> Original commit message:
>  commit 1289f7f15001c7ed36be6d23cb145c1d5feacdc8
>  Author: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>  Date:   Wed Nov 6 11:35:50 2019 +0900
> 
>   iommu/ipmmu-vmsa: Add utlb_offset_base
> 
>   Since we will have changed memory mapping of the IPMMU in the future,
>   this patch adds a utlb_offset_base into struct ipmmu_features
>   for IMUCTR and IMUASID registers. No behavior change.
> 
>   Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>   Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>   Signed-off-by: Joerg Roedel <jroedel@suse.de>
> 
> **********
> 
> This is a prereq work needed to add support for S4 series easily
> in the future.
> 
> Almost the same change as original commit makes, but without updating
> struct ipmmu_features_default which Xen driver doesn't have (there is
> no support of old Arm32 based Gen2 SoCs).
> 
> No change in behavior.
> 
> Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda
diff mbox series

Patch

diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
index ca33456..d8f96fc 100644
--- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
+++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
@@ -111,6 +111,7 @@  struct ipmmu_features {
     unsigned int num_utlbs;
     unsigned int ctx_offset_base;
     unsigned int ctx_offset_stride;
+    unsigned int utlb_offset_base;
 };
 
 /* Root/Cache IPMMU device's information */
@@ -374,7 +375,7 @@  static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
 
 static uint32_t ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, uint32_t reg)
 {
-    return reg;
+    return mmu->features->utlb_offset_base + reg;
 }
 
 static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu,
@@ -738,6 +739,7 @@  static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
     .num_utlbs = 48,
     .ctx_offset_base = 0,
     .ctx_offset_stride = 0x40,
+    .utlb_offset_base = 0,
 };
 
 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)