| Message ID | 20160606055638.475-1-haozhong.zhang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 06.06.16 at 07:56, <haozhong.zhang@intel.com> wrote: > This reverts commit cfacce340608be5f94ce0c8f424487b63c3d5399. > > Platforms supporting Intel NVDIMM are now required to provide > persistency once pmem stores are accepted by the memory subsystem. > This is usually achieved by a platform-level feature known as ADR > (Asynchronous DRAM Refresh) that flushes any memory subsystem write > pending queues on power loss/shutdown. Therefore, the pcommit > instruction, which has not yet shipped on any product (and will not), > is no longer needed and is deprecated. > > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> Acked-by: Jan Beulich <jbeulich@suse.com> Wei - certainly something to consider for 4.7. Jan
On Mon, Jun 06, 2016 at 02:54:47AM -0600, Jan Beulich wrote: > >>> On 06.06.16 at 07:56, <haozhong.zhang@intel.com> wrote: > > This reverts commit cfacce340608be5f94ce0c8f424487b63c3d5399. > > > > Platforms supporting Intel NVDIMM are now required to provide > > persistency once pmem stores are accepted by the memory subsystem. > > This is usually achieved by a platform-level feature known as ADR > > (Asynchronous DRAM Refresh) that flushes any memory subsystem write > > pending queues on power loss/shutdown. Therefore, the pcommit > > instruction, which has not yet shipped on any product (and will not), > > is no longer needed and is deprecated. > > > > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> > > Acked-by: Jan Beulich <jbeulich@suse.com> > > Wei - certainly something to consider for 4.7. > Sure. No point in shipping feature that won't show up in hardware. Release-acked-by: Wei Liu <wei.liu2@citrix.com> But please wait a bit before committing while we try to sort out RC5 and branching etc. Wei. > Jan >
>>> On 06.06.16 at 12:31, <wei.liu2@citrix.com> wrote: > On Mon, Jun 06, 2016 at 02:54:47AM -0600, Jan Beulich wrote: >> >>> On 06.06.16 at 07:56, <haozhong.zhang@intel.com> wrote: >> > This reverts commit cfacce340608be5f94ce0c8f424487b63c3d5399. >> > >> > Platforms supporting Intel NVDIMM are now required to provide >> > persistency once pmem stores are accepted by the memory subsystem. >> > This is usually achieved by a platform-level feature known as ADR >> > (Asynchronous DRAM Refresh) that flushes any memory subsystem write >> > pending queues on power loss/shutdown. Therefore, the pcommit >> > instruction, which has not yet shipped on any product (and will not), >> > is no longer needed and is deprecated. >> > >> > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> >> >> Acked-by: Jan Beulich <jbeulich@suse.com> >> >> Wei - certainly something to consider for 4.7. >> > > Sure. No point in shipping feature that won't show up in hardware. > > Release-acked-by: Wei Liu <wei.liu2@citrix.com> > > But please wait a bit before committing while we try to sort out RC5 and > branching etc. Sure. Got to wait for a VMX maintainer ack anyway. Jan
> From: Jan Beulich [mailto:JBeulich@suse.com] > Sent: Monday, June 06, 2016 6:38 PM > > >>> On 06.06.16 at 12:31, <wei.liu2@citrix.com> wrote: > > On Mon, Jun 06, 2016 at 02:54:47AM -0600, Jan Beulich wrote: > >> >>> On 06.06.16 at 07:56, <haozhong.zhang@intel.com> wrote: > >> > This reverts commit cfacce340608be5f94ce0c8f424487b63c3d5399. > >> > > >> > Platforms supporting Intel NVDIMM are now required to provide > >> > persistency once pmem stores are accepted by the memory subsystem. > >> > This is usually achieved by a platform-level feature known as ADR > >> > (Asynchronous DRAM Refresh) that flushes any memory subsystem write > >> > pending queues on power loss/shutdown. Therefore, the pcommit > >> > instruction, which has not yet shipped on any product (and will not), > >> > is no longer needed and is deprecated. > >> > > >> > Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> > >> > >> Acked-by: Jan Beulich <jbeulich@suse.com> > >> > >> Wei - certainly something to consider for 4.7. > >> > > > > Sure. No point in shipping feature that won't show up in hardware. > > > > Release-acked-by: Wei Liu <wei.liu2@citrix.com> > > > > But please wait a bit before committing while we try to sort out RC5 and > > branching etc. > > Sure. Got to wait for a VMX maintainer ack anyway. > Here it is: Acked-by: Kevin Tian <kevin.tian@intel.com>
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index e1e0e44..38e34bd 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -174,9 +174,6 @@ static void __init calculate_hvm_featureset(void) if ( !cpu_has_vmx_xsaves ) __clear_bit(X86_FEATURE_XSAVES, hvm_featureset); - - if ( !cpu_has_vmx_pcommit ) - __clear_bit(X86_FEATURE_PCOMMIT, hvm_featureset); } sanitise_featureset(hvm_featureset); diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 8284281..f06a96b 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -244,7 +244,6 @@ static int vmx_init_vmcs_config(void) SECONDARY_EXEC_ENABLE_VM_FUNCTIONS | SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS | SECONDARY_EXEC_XSAVES | - SECONDARY_EXEC_PCOMMIT | SECONDARY_EXEC_TSC_SCALING); rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); if ( _vmx_misc_cap & VMX_MISC_VMWRITE_ALL ) @@ -1079,12 +1078,6 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(PLE_WINDOW, ple_window); } - /* - * We do not intercept pcommit for L1 guest and allow L1 hypervisor to - * intercept pcommit for L2 guest (see nvmx_n2_vmexit_handler()). - */ - v->arch.hvm_vmx.secondary_exec_control &= ~SECONDARY_EXEC_PCOMMIT; - if ( cpu_has_vmx_secondary_exec_control ) __vmwrite(SECONDARY_VM_EXEC_CONTROL, v->arch.hvm_vmx.secondary_exec_control); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 743b5a1..45ab24e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3759,7 +3759,6 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) case EXIT_REASON_ACCESS_LDTR_OR_TR: case EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED: case EXIT_REASON_INVPCID: - case EXIT_REASON_PCOMMIT: /* fall through */ default: exit_and_crash: diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index faa8b69..3bf7d6b 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1900,8 +1900,6 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) SECONDARY_EXEC_ENABLE_VPID | SECONDARY_EXEC_UNRESTRICTED_GUEST | SECONDARY_EXEC_ENABLE_EPT; - if ( cpu_has_vmx_pcommit ) - data |= SECONDARY_EXEC_PCOMMIT; data = gen_vmx_msr(data, 0, host_data); break; case MSR_IA32_VMX_EXIT_CTLS: @@ -2182,7 +2180,6 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *regs, case EXIT_REASON_VMXON: case EXIT_REASON_INVEPT: case EXIT_REASON_XSETBV: - case EXIT_REASON_PCOMMIT: /* inject to L1 */ nvcpu->nv_vmexit_pending = 1; break; diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index b54f52f..8e15489 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -307,7 +307,6 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_ENABLE_PML 0x00020000 #define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 #define SECONDARY_EXEC_XSAVES 0x00100000 -#define SECONDARY_EXEC_PCOMMIT 0x00200000 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 extern u32 vmx_secondary_exec_control; @@ -378,8 +377,6 @@ extern u64 vmx_ept_vpid_cap; (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_PML) #define cpu_has_vmx_xsaves \ (vmx_secondary_exec_control & SECONDARY_EXEC_XSAVES) -#define cpu_has_vmx_pcommit \ - (vmx_secondary_exec_control & SECONDARY_EXEC_PCOMMIT) #define cpu_has_vmx_tsc_scaling \ (vmx_secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) diff --git a/xen/include/asm-x86/hvm/vmx/vmx.h b/xen/include/asm-x86/hvm/vmx/vmx.h index a85d488..359b2a9 100644 --- a/xen/include/asm-x86/hvm/vmx/vmx.h +++ b/xen/include/asm-x86/hvm/vmx/vmx.h @@ -213,7 +213,6 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) #define EXIT_REASON_PML_FULL 62 #define EXIT_REASON_XSAVES 63 #define EXIT_REASON_XRSTORS 64 -#define EXIT_REASON_PCOMMIT 65 /* * Interruption-information format diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index b506d6c..39acf8c 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -209,7 +209,6 @@ XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ -XEN_CPUFEATURE(PCOMMIT, 5*32+22) /*A PCOMMIT instruction */ XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */
This reverts commit cfacce340608be5f94ce0c8f424487b63c3d5399. Platforms supporting Intel NVDIMM are now required to provide persistency once pmem stores are accepted by the memory subsystem. This is usually achieved by a platform-level feature known as ADR (Asynchronous DRAM Refresh) that flushes any memory subsystem write pending queues on power loss/shutdown. Therefore, the pcommit instruction, which has not yet shipped on any product (and will not), is no longer needed and is deprecated. Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com> --- xen/arch/x86/cpuid.c | 3 --- xen/arch/x86/hvm/vmx/vmcs.c | 7 ------- xen/arch/x86/hvm/vmx/vmx.c | 1 - xen/arch/x86/hvm/vmx/vvmx.c | 3 --- xen/include/asm-x86/hvm/vmx/vmcs.h | 3 --- xen/include/asm-x86/hvm/vmx/vmx.h | 1 - xen/include/public/arch-x86/cpufeatureset.h | 1 - 7 files changed, 19 deletions(-)