From patchwork Mon Jun 6 05:56:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9157261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8127560572 for ; Mon, 6 Jun 2016 06:00:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6705925EA6 for ; Mon, 6 Jun 2016 06:00:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 58C9126C9B; Mon, 6 Jun 2016 06:00:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3D3A525EA6 for ; Mon, 6 Jun 2016 06:00:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b9nXg-0001Ww-HK; Mon, 06 Jun 2016 05:57:40 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1b9nXf-0001Wq-2a for xen-devel@lists.xen.org; Mon, 06 Jun 2016 05:57:39 +0000 Received: from [85.158.137.68] by server-11.bemta-3.messagelabs.com id 90/CC-10668-2D015575; Mon, 06 Jun 2016 05:57:38 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsXS1tYhontRIDT c4Mc1DYslHxezODB6HN39mymAMYo1My8pvyKBNeNvxzX2gof6FfsXXGNvYJyl1sXIySEkUCmx te0HK4gtIcArcWTZDCjbX2Lio0/sXYxcQDU9jBI7v0xnBkmwCehLrHh8EKxIREBa4trny4wgR cwCxxklWv/PYQdJCAu4SSzqew7WwCKgKrHo3w5GEJtXwFriSv81dogNchKTF19inMDIvYCRYR WjenFqUVlqka6FXlJRZnpGSW5iZo6uoYGxXm5qcXFiempOYlKxXnJ+7iZGoH8ZgGAH44V250O MkhxMSqK8sl9DwoX4kvJTKjMSizPii0pzUosPMcpwcChJ8M7mDw0XEixKTU+tSMvMAQYaTFqC g0dJhNcYJM1bXJCYW5yZDpE6xagoJc67DSQhAJLIKM2Da4MF9yVGWSlhXkagQ4R4ClKLcjNLU OVfMYpzMCoJ8/aATOHJzCuBm/4KaDET0OJl14JBFpckIqSkGhjjTK48PXc77/1SGa39Vca7td Mdngj6hc9OObTJZ5rDPo/tPKvFPab6Ht8rPO2hkvLePI1P3P4aUWen+f5bLTXts/+GaXcW9As Ydmt6sPsvKOTjmXLR6IzguQkTtObNmLz64cSVRT1ZW/M3u89+Ktcl7bZo90eTyIzqrH86ZoXv Ci9unpasfj5SiaU4I9FQi7moOBEAIoWxB2kCAAA= X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-7.tower-31.messagelabs.com!1465192656!36314931!1 X-Originating-IP: [134.134.136.20] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogMTM0LjEzNC4xMzYuMjAgPT4gMzU1MzU4\n X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 42931 invoked from network); 6 Jun 2016 05:57:37 -0000 Received: from mga02.intel.com (HELO mga02.intel.com) (134.134.136.20) by server-7.tower-31.messagelabs.com with SMTP; 6 Jun 2016 05:57:37 -0000 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP; 05 Jun 2016 22:57:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,425,1459839600"; d="scan'208";a="714500604" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.13.126]) by FMSMGA003.fm.intel.com with ESMTP; 05 Jun 2016 22:57:34 -0700 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Mon, 6 Jun 2016 13:56:38 +0800 Message-Id: <20160606055638.475-1-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.8.3 Cc: Andrew Cooper , Kevin Tian , Jun Nakajima , Jan Beulich , Haozhong Zhang Subject: [Xen-devel] [PATCH] Revert "x86/hvm: add support for pcommit instruction" X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP This reverts commit cfacce340608be5f94ce0c8f424487b63c3d5399. Platforms supporting Intel NVDIMM are now required to provide persistency once pmem stores are accepted by the memory subsystem. This is usually achieved by a platform-level feature known as ADR (Asynchronous DRAM Refresh) that flushes any memory subsystem write pending queues on power loss/shutdown. Therefore, the pcommit instruction, which has not yet shipped on any product (and will not), is no longer needed and is deprecated. Signed-off-by: Haozhong Zhang Acked-by: Jan Beulich Acked-by: Kevin Tian --- xen/arch/x86/cpuid.c | 3 --- xen/arch/x86/hvm/vmx/vmcs.c | 7 ------- xen/arch/x86/hvm/vmx/vmx.c | 1 - xen/arch/x86/hvm/vmx/vvmx.c | 3 --- xen/include/asm-x86/hvm/vmx/vmcs.h | 3 --- xen/include/asm-x86/hvm/vmx/vmx.h | 1 - xen/include/public/arch-x86/cpufeatureset.h | 1 - 7 files changed, 19 deletions(-) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index e1e0e44..38e34bd 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -174,9 +174,6 @@ static void __init calculate_hvm_featureset(void) if ( !cpu_has_vmx_xsaves ) __clear_bit(X86_FEATURE_XSAVES, hvm_featureset); - - if ( !cpu_has_vmx_pcommit ) - __clear_bit(X86_FEATURE_PCOMMIT, hvm_featureset); } sanitise_featureset(hvm_featureset); diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 8284281..f06a96b 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -244,7 +244,6 @@ static int vmx_init_vmcs_config(void) SECONDARY_EXEC_ENABLE_VM_FUNCTIONS | SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS | SECONDARY_EXEC_XSAVES | - SECONDARY_EXEC_PCOMMIT | SECONDARY_EXEC_TSC_SCALING); rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); if ( _vmx_misc_cap & VMX_MISC_VMWRITE_ALL ) @@ -1079,12 +1078,6 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(PLE_WINDOW, ple_window); } - /* - * We do not intercept pcommit for L1 guest and allow L1 hypervisor to - * intercept pcommit for L2 guest (see nvmx_n2_vmexit_handler()). - */ - v->arch.hvm_vmx.secondary_exec_control &= ~SECONDARY_EXEC_PCOMMIT; - if ( cpu_has_vmx_secondary_exec_control ) __vmwrite(SECONDARY_VM_EXEC_CONTROL, v->arch.hvm_vmx.secondary_exec_control); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 743b5a1..45ab24e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3759,7 +3759,6 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) case EXIT_REASON_ACCESS_LDTR_OR_TR: case EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED: case EXIT_REASON_INVPCID: - case EXIT_REASON_PCOMMIT: /* fall through */ default: exit_and_crash: diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index faa8b69..3bf7d6b 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1900,8 +1900,6 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) SECONDARY_EXEC_ENABLE_VPID | SECONDARY_EXEC_UNRESTRICTED_GUEST | SECONDARY_EXEC_ENABLE_EPT; - if ( cpu_has_vmx_pcommit ) - data |= SECONDARY_EXEC_PCOMMIT; data = gen_vmx_msr(data, 0, host_data); break; case MSR_IA32_VMX_EXIT_CTLS: @@ -2182,7 +2180,6 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *regs, case EXIT_REASON_VMXON: case EXIT_REASON_INVEPT: case EXIT_REASON_XSETBV: - case EXIT_REASON_PCOMMIT: /* inject to L1 */ nvcpu->nv_vmexit_pending = 1; break; diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h index b54f52f..8e15489 100644 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h @@ -307,7 +307,6 @@ extern u32 vmx_vmentry_control; #define SECONDARY_EXEC_ENABLE_PML 0x00020000 #define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000 #define SECONDARY_EXEC_XSAVES 0x00100000 -#define SECONDARY_EXEC_PCOMMIT 0x00200000 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 extern u32 vmx_secondary_exec_control; @@ -378,8 +377,6 @@ extern u64 vmx_ept_vpid_cap; (vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_PML) #define cpu_has_vmx_xsaves \ (vmx_secondary_exec_control & SECONDARY_EXEC_XSAVES) -#define cpu_has_vmx_pcommit \ - (vmx_secondary_exec_control & SECONDARY_EXEC_PCOMMIT) #define cpu_has_vmx_tsc_scaling \ (vmx_secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) diff --git a/xen/include/asm-x86/hvm/vmx/vmx.h b/xen/include/asm-x86/hvm/vmx/vmx.h index a85d488..359b2a9 100644 --- a/xen/include/asm-x86/hvm/vmx/vmx.h +++ b/xen/include/asm-x86/hvm/vmx/vmx.h @@ -213,7 +213,6 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc) #define EXIT_REASON_PML_FULL 62 #define EXIT_REASON_XSAVES 63 #define EXIT_REASON_XRSTORS 64 -#define EXIT_REASON_PCOMMIT 65 /* * Interruption-information format diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index b506d6c..39acf8c 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -209,7 +209,6 @@ XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ -XEN_CPUFEATURE(PCOMMIT, 5*32+22) /*A PCOMMIT instruction */ XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */