From patchwork Thu Dec 22 18:24:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9485473 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 16BAE600BA for ; Thu, 22 Dec 2016 18:26:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE1A52843F for ; Thu, 22 Dec 2016 18:26:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E2F962844B; Thu, 22 Dec 2016 18:26:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5F7352843F for ; Thu, 22 Dec 2016 18:26:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cK82P-0005to-Df; Thu, 22 Dec 2016 18:24:21 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cK82N-0005o6-Kc for xen-devel@lists.xenproject.org; Thu, 22 Dec 2016 18:24:19 +0000 Received: from [85.158.139.211] by server-15.bemta-5.messagelabs.com id 5B/6D-06501-35A1C585; Thu, 22 Dec 2016 18:24:19 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTTdIKib CYOlZHovvWyYzOTB6HP5whSWAMYo1My8pvyKBNaP9yU72grcyFR9vPGdvYPwg2sXIxSEksJlR 4kfbSmYIZzmjxOn7jxm7GDk52AR0JXbcfM0MYosIhEo8XfAdyObgYBbwkvjy3hskLCxgLXFh2 hGwchYBVYl7/w+yg9i8AjYS01ZNZAOxJQTkJBrO3wcbwwkUf/V1EhOILQTUe3DiDuYJjNwLGB lWMaoXpxaVpRbpmuglFWWmZ5TkJmbm6BoamOrlphYXJ6an5iQmFesl5+duYgR6lwEIdjDe6nM +xCjJwaQkypvDGxMhxJeUn1KZkVicEV9UmpNafIhRhoNDSYL3tARQTrAoNT21Ii0zBxhmMGkJ Dh4lEV4mSaA0b3FBYm5xZjpE6hSjopQ4712QPgGQREZpHlwbLLQvMcpKCfMyAh0ixFOQWpSbW YIq/4pRnINRSZj3AsgUnsy8Erjpr4AWMwEttm2OBllckoiQkmpgZNzbf5zRJzXM+a9CtNVaPZ 91hxcqXD7x26n2n5yup0bTj0Obm8XuVLbEnpxRWPHO2+56xoEz32a5KjUZ9go/tbSr2bxkkZu G6duoGXYpdpfPxe/lfmFzSP5SmuY9Dau57LKyjlXX751km7eQ1aRy75/OBWrttwMk/y6exs6r 675NpnAXSxmfEktxRqKhFnNRcSIAfD6koGgCAAA= X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-11.tower-206.messagelabs.com!1482431057!64727331!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 15190 invoked from network); 22 Dec 2016 18:24:17 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-11.tower-206.messagelabs.com with SMTP; 22 Dec 2016 18:24:17 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D1311500; Thu, 22 Dec 2016 10:24:17 -0800 (PST) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5C6FD3F220; Thu, 22 Dec 2016 10:24:16 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Thu, 22 Dec 2016 18:24:42 +0000 Message-Id: <20161222182446.18791-23-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20161222182446.18791-1-andre.przywara@arm.com> References: <20161222182446.18791-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijay Kilari Subject: [Xen-devel] [RFC PATCH v2 22/26] ARM: vITS: handle INV command X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The INV command instructs the ITS to update the configuration data for a given LPI by re-reading its entry from the property table. We don't need to care so much about the priority value, but enabling or disabling an LPI has some effect: We remove or push virtual LPIs to their VCPUs, also check the virtual pending bit if an LPI gets enabled. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-its.c | 2 +- xen/arch/arm/vgic-its.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-its.c b/xen/arch/arm/gic-its.c index 1da28b9..7dbb9e6 100644 --- a/xen/arch/arm/gic-its.c +++ b/xen/arch/arm/gic-its.c @@ -248,7 +248,7 @@ static uint64_t encode_phys_addr(paddr_t addr, int page_bits) { uint64_t ret; - if ( page_bits < 16) + if ( page_bits < 16 ) return (uint64_t)addr & GENMASK(47, page_bits); ret = addr & GENMASK(47, 16); diff --git a/xen/arch/arm/vgic-its.c b/xen/arch/arm/vgic-its.c index 52c660a..bcabb04 100644 --- a/xen/arch/arm/vgic-its.c +++ b/xen/arch/arm/vgic-its.c @@ -228,6 +228,75 @@ out_unlock: return ret; } +/* For a given virtual LPI read the enabled bit from the virtual property + * table and update the virtual IRQ's state. + * This takes care of removing or pushing of virtual LPIs to their VCPUs. + */ +static void update_lpi_enabled_status(struct virt_its* its, + struct vcpu *vcpu, uint32_t vlpi) +{ + struct pending_irq *pirq = lpi_to_pending(vcpu, vlpi, false); + uint8_t property = its->d->arch.vgic.proptable[vlpi - 8192]; + + if ( property & LPI_PROP_ENABLED ) + { + if ( pirq ) + { + unsigned long flags; + + set_bit(GIC_IRQ_GUEST_ENABLED, &pirq->status); + spin_lock_irqsave(&vcpu->arch.vgic.lock, flags); + if ( !list_empty(&pirq->inflight) && + !test_bit(GIC_IRQ_GUEST_VISIBLE, &pirq->status) ) + gic_raise_guest_irq(vcpu, vlpi, property & 0xfc); + spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags); + } + + /* Check whether the LPI has fired while the guest had it disabled. */ + if (test_and_clear_bit(vlpi - 8192, vcpu->arch.vgic.pendtable)) + vgic_vcpu_inject_irq(vcpu, vlpi); + } + else + { + if ( pirq ) + { + clear_bit(GIC_IRQ_GUEST_ENABLED, &pirq->status); + gic_remove_from_queues(vcpu, vlpi); + } + } +} + +static int its_handle_inv(struct virt_its *its, uint64_t *cmdptr) +{ + uint32_t devid = its_cmd_get_deviceid(cmdptr); + uint32_t eventid = its_cmd_get_id(cmdptr); + struct vits_itte *itte; + struct vcpu *vcpu; + uint32_t vlpi; + int ret = -1; + + spin_lock(&its->its_lock); + + itte = get_devid_evid(its, devid, eventid); + if ( !itte ) + goto out_unlock; + + vcpu = its->d->vcpu[itte->collection]; + vlpi = itte->vlpi; + + ret = 0; + + put_devid_evid(its, itte); + +out_unlock: + spin_unlock(&its->its_lock); + + if ( !ret ) + update_lpi_enabled_status(its, vcpu, vlpi); + + return ret; +} + static int its_handle_mapc(struct virt_its *its, uint64_t *cmdptr) { uint32_t collid = its_cmd_get_collection(cmdptr); @@ -418,6 +487,9 @@ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its, case GITS_CMD_INT: its_handle_int(its, cmdptr); break; + case GITS_CMD_INV: + its_handle_inv(its, cmdptr); + break; case GITS_CMD_MAPC: its_handle_mapc(its, cmdptr); break;