From patchwork Fri Jan 27 16:45:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamas Lengyel X-Patchwork-Id: 9542301 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 270CE604A0 for ; Fri, 27 Jan 2017 16:48:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17DCD27F54 for ; Fri, 27 Jan 2017 16:48:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0BAF027FBB; Fri, 27 Jan 2017 16:48:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CF50327F54 for ; Fri, 27 Jan 2017 16:48:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cX9f7-00026h-7H; Fri, 27 Jan 2017 16:46:09 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cX9f5-00026a-Sb for xen-devel@lists.xenproject.org; Fri, 27 Jan 2017 16:46:08 +0000 Received: from [85.158.139.211] by server-17.bemta-5.messagelabs.com id 09/7B-12366-E497B885; Fri, 27 Jan 2017 16:46:06 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeJIrShJLcpLzFFi42Lxqg121PWr7I4 wWP2ey+L7lslMDowehz9cYQlgjGLNzEvKr0hgzdg/bRJ7wXf9igd7WtgbGN+qdTFycQgJzGCU uHDwA0sXIycHi8AbFoltzx1BEhIC71gk9v18zA6SkBCIkfj9/g4LhF0p8axtAxOILSSgKXFww xlmiEmTmCTWvHzOBpJgEzCSuHq1B8wWEVCSuLdqMhNIEbPAOUaJ670LgBIcHMICYRL3zqZAbF aV+Lj3JdgyXgE7iV+996EWy0vsarvIOoGRbwEjwypGjeLUorLUIl0jQ72kosz0jJLcxMwcXUM DU73c1OLixPTUnMSkYr3k/NxNjMBQqWdgYNzBeHey3yFGSQ4mJVFebovuCCG+pPyUyozE4oz4 otKc1OJDjDIcHEoSvG/KgXKCRanpqRVpmTnAoIVJS3DwKInwKlYApXmLCxJzizPTIVKnGHU5d u26/JJJiCUvPy9VSpyXGaRIAKQoozQPbgQsgi4xykoJ8zIyMDAI8RSkFuVmlqDKv2IU52BUEu Z1BZnCk5lXArfpFdARTEBHiP/oAjmiJBEhJdXAaPHY8alQ+dqrO3RbORUWnFmuPmX92b33u01 rFMIkwn6w35jJxiLfvFBcZ4+B/Mebvd+9GbZ3Pfit/Ozexfw121OL3nQlOd5meZn6MWTh00Ol CTMuXFlov/550tVtVba5czqT7GI4T57mT1i+X7hkw9JmsSffyw+uu/Lm8jTNP+cYojtmCQX+3 qfEUpyRaKjFXFScCAD3HZPEmwIAAA== X-Env-Sender: tamas.lengyel@zentific.com X-Msg-Ref: server-8.tower-206.messagelabs.com!1485535564!81974266!1 X-Originating-IP: [74.125.83.65] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 13281 invoked from network); 27 Jan 2017 16:46:05 -0000 Received: from mail-pg0-f65.google.com (HELO mail-pg0-f65.google.com) (74.125.83.65) by server-8.tower-206.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 27 Jan 2017 16:46:05 -0000 Received: by mail-pg0-f65.google.com with SMTP id 204so25387729pge.2 for ; Fri, 27 Jan 2017 08:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zentific-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=bjvnicg1pLIXHvk+C7Cd9E4OXqkMqooZfg1GSB4tHac=; b=LixTZ8v0evd4XYfB22sfPMF3CzRewpnu+82u6kWmlX0QIgz7krsY2krOxrYCoLAThc k3uDbAZqynHGBpCt8kgepRV2ImGHKsiwbA5IzwyR9pdkbO92BoO6ORoj61mOkoGbFBXt t3ZgyOHynjM/eNyZN3U7p+RwFCM/1Rl1C/IFrhYPyqYWYNzsFk9gjnd0wZpSJqwfIOHO 6YARGROXpMi8QOhrc9P/Hajywx45OH6Jf2szGBtprVwHW9EFUKkoOg9xEmuBH7z19y8b BqiGCQ9rObNcsMNHQfE6plhaGX9l8bVK0GlbKfiKjQGl9opOomY/hiK8mJL7XFZrma4/ 2FmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bjvnicg1pLIXHvk+C7Cd9E4OXqkMqooZfg1GSB4tHac=; b=AMvRPczsCF303cuoI1o5u8S5m/ftbgxJUqsa8v5YCHx7RcMwKWdtoioee99GDJYqJp 7RikswUhlsc/Z53f0UdAVRATP5P9sETKmSTH+Fp7YNteC7W5RUHSXaIxkttm0RZwqjgA Bj4dEYetndmM0R2LbyHgSZn3EIQ9t8+vg0+7zPsei+TAuKjV4ml30pvawloWlje6bNDv LTsYBACVt12xKN3ZmnOhM9KudfDP0IQ/XJZmGai71nu/5x6gq6mECZrkycZJWfYeMKR6 mdtpA8Zqbk5tXJDQU5qpmr7qW00z2yJVnGMIyqGUYCc/W6SmW7LefmX54L2VUr56biPg eoYw== X-Gm-Message-State: AIkVDXLT/re4E/nVqKiPUNnqduHD0Pluj+AT5rgikPyuuLZOZuW3HfEqWbLX8TBlfycyfw== X-Received: by 10.99.125.17 with SMTP id y17mr10710908pgc.27.1485535564260; Fri, 27 Jan 2017 08:46:04 -0800 (PST) Received: from l1.lan (c-73-14-35-59.hsd1.co.comcast.net. [73.14.35.59]) by smtp.gmail.com with ESMTPSA id g70sm12628772pfb.50.2017.01.27.08.45.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 08:46:03 -0800 (PST) From: Tamas K Lengyel To: xen-devel@lists.xenproject.org Date: Fri, 27 Jan 2017 09:45:45 -0700 Message-Id: <20170127164545.6945-1-tamas.lengyel@zentific.com> X-Mailer: git-send-email 2.11.0 Cc: Tamas K Lengyel , Julien Grall , Stefano Stabellini , Ian Jackson , Wei Liu Subject: [Xen-devel] [PATCH v2] xen/arm: flush icache as well when XEN_DOMCTL_cacheflush is issued X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP When the toolstack modifies memory of a running ARM VM it may happen that the underlying memory of a current vCPU PC is changed. Without flushing the icache the vCPU may continue executing stale instructions. In this patch we introduce VA-based icache flushing macros. Also expose the xc_domain_cacheflush through xenctrl.h. Signed-off-by: Tamas K Lengyel Acked-by: Wei Liu --- Cc: Ian Jackson Cc: Wei Liu Cc: Stefano Stabellini Cc: Julien Grall Note: patch has been verified to solve stale icache issues on the HiKey platform. v2: Return 0 on x86 and clarify comment in xenctrl.h --- tools/libxc/include/xenctrl.h | 8 ++++++++ tools/libxc/xc_domain.c | 6 +++--- tools/libxc/xc_private.h | 3 --- xen/arch/arm/mm.c | 1 + xen/include/asm-arm/arm32/page.h | 3 +++ xen/include/asm-arm/arm64/page.h | 3 +++ xen/include/asm-arm/page.h | 31 +++++++++++++++++++++++++++++++ 7 files changed, 49 insertions(+), 6 deletions(-) diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h index 63c616ff6a..a2f23fcd5a 100644 --- a/tools/libxc/include/xenctrl.h +++ b/tools/libxc/include/xenctrl.h @@ -2720,6 +2720,14 @@ int xc_livepatch_revert(xc_interface *xch, char *name, uint32_t timeout); int xc_livepatch_unload(xc_interface *xch, char *name, uint32_t timeout); int xc_livepatch_replace(xc_interface *xch, char *name, uint32_t timeout); +/* + * Ensure cache coherency after memory modifications. A call to this function + * is only required on ARM as the x86 architecture provides cache coherency + * guarantees. Calling this function on x86 is allowed but has no effect. + */ +int xc_domain_cacheflush(xc_interface *xch, uint32_t domid, + xen_pfn_t start_pfn, xen_pfn_t nr_pfns); + /* Compat shims */ #include "xenctrl_compat.h" diff --git a/tools/libxc/xc_domain.c b/tools/libxc/xc_domain.c index 296b8523b5..98ab6ba3fd 100644 --- a/tools/libxc/xc_domain.c +++ b/tools/libxc/xc_domain.c @@ -74,10 +74,10 @@ int xc_domain_cacheflush(xc_interface *xch, uint32_t domid, /* * The x86 architecture provides cache coherency guarantees which prevent * the need for this hypercall. Avoid the overhead of making a hypercall - * just for Xen to return -ENOSYS. + * just for Xen to return -ENOSYS. It is safe to ignore this call on x86 + * so we just return 0. */ - errno = ENOSYS; - return -1; + return 0; #else DECLARE_DOMCTL; domctl.cmd = XEN_DOMCTL_cacheflush; diff --git a/tools/libxc/xc_private.h b/tools/libxc/xc_private.h index 97445ae1fe..fddebdc917 100644 --- a/tools/libxc/xc_private.h +++ b/tools/libxc/xc_private.h @@ -366,9 +366,6 @@ void bitmap_byte_to_64(uint64_t *lp, const uint8_t *bp, int nbits); /* Optionally flush file to disk and discard page cache */ void discard_file_cache(xc_interface *xch, int fd, int flush); -int xc_domain_cacheflush(xc_interface *xch, uint32_t domid, - xen_pfn_t start_pfn, xen_pfn_t nr_pfns); - #define MAX_MMU_UPDATES 1024 struct xc_mmu { mmu_update_t updates[MAX_MMU_UPDATES]; diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 99588a330d..43e5b3d9e2 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -389,6 +389,7 @@ void flush_page_to_ram(unsigned long mfn) void *v = map_domain_page(_mfn(mfn)); clean_and_invalidate_dcache_va_range(v, PAGE_SIZE); + invalidate_icache_va_range(v, PAGE_SIZE); unmap_domain_page(v); } diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index ea4b312c70..10e5288d0f 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -19,6 +19,9 @@ static inline void write_pte(lpae_t *p, lpae_t pte) : : "r" (pte.bits), "r" (p) : "memory"); } +/* Inline ASM to invalidate icache on register R (may be an inline asm operand) */ +#define __invalidate_icache_one(R) STORE_CP32(R, ICIMVAU) + /* Inline ASM to invalidate dcache on register R (may be an inline asm operand) */ #define __invalidate_dcache_one(R) STORE_CP32(R, DCIMVAC) diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 23d778154d..0f380b95b4 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -16,6 +16,9 @@ static inline void write_pte(lpae_t *p, lpae_t pte) : : "r" (pte.bits), "r" (p) : "memory"); } +/* Inline ASM to invalidate icache on register R (may be an inline asm operand) */ +#define __invalidate_icache_one(R) "ic ivau, %" #R ";" + /* Inline ASM to invalidate dcache on register R (may be an inline asm operand) */ #define __invalidate_dcache_one(R) "dc ivac, %" #R ";" diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index c492d6df50..a618d0e556 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -371,6 +371,37 @@ static inline int clean_and_invalidate_dcache_va_range : : "r" (_p), "m" (*_p)); \ } while (0) +static inline int invalidate_icache_va_range(const void *p, unsigned long size) +{ + size_t off; + const void *end = p + size; + + dsb(sy); /* So the CPU issues all writes to the range */ + + off = (unsigned long)p % cacheline_bytes; + if ( off ) + { + p -= off; + asm volatile (__invalidate_icache_one(0) : : "r" (p)); + p += cacheline_bytes; + size -= cacheline_bytes - off; + } + off = (unsigned long)end % cacheline_bytes; + if ( off ) + { + end -= off; + size -= off; + asm volatile (__invalidate_icache_one(0) : : "r" (end)); + } + + for ( ; p < end; p += cacheline_bytes ) + asm volatile (__invalidate_icache_one(0) : : "r" (p)); + + dsb(sy); /* So we know the flushes happen before continuing */ + + return 0; +} + /* * Flush a range of VA's hypervisor mappings from the data TLB of the * local processor. This is not sufficient when changing code mappings