From patchwork Mon Jan 30 18:31:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9545891 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3AE1160415 for ; Mon, 30 Jan 2017 18:33:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3234527F82 for ; Mon, 30 Jan 2017 18:33:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2719028173; Mon, 30 Jan 2017 18:33:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C755527F7F for ; Mon, 30 Jan 2017 18:33:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cYGj0-0007f1-25; Mon, 30 Jan 2017 18:30:46 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cYGiy-0007dA-3r for xen-devel@lists.xenproject.org; Mon, 30 Jan 2017 18:30:44 +0000 Received: from [85.158.139.211] by server-15.bemta-5.messagelabs.com id A0/0B-06501-3568F885; Mon, 30 Jan 2017 18:30:43 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTTeorT/ C4NRBK4vvWyYzOTB6HP5whSWAMYo1My8pvyKBNaO74Q5bQZ9MxfS385kbGOeIdTFycQgJbGaU mPfgFDuEs5xRYvKs7cxdjJwcbAK6EjtuvgazRQRCJeb8fARkc3AwC3hJfHnvDRIWFrCVeHS8n xXEZhFQlXj28zZYOa+AtcTLw2vAbAkBOYmG8/fBbE4BG4nZm38zgdhCQDX/epYzTmDkXsDIsI pRozi1qCy1SNfYQC+pKDM9oyQ3MTNH19DAVC83tbg4MT01JzGpWC85P3cTI9C/9QwMjDsYJ6z yO8QoycGkJMrb97EvQogvKT+lMiOxOCO+qDQntfgQowwHh5IEr1Rrf4SQYFFqempFWmYOMNBg 0hIcPEoivBtbgNK8xQWJucWZ6RCpU4yKUuK8P0ASAiCJjNI8uDZYcF9ilJUS5mVkYGAQ4ilIL crNLEGVf8UozsGoJMx7E2QKT2ZeCdz0V0CLmYAWu7/qA1lckoiQkmpgXPHwdgtjdEa4Uu/udQ 37RO7djuNxD6zV9/yxpbn4itjaEKZeZeUDbOVVzyL2GPJMW2MgOUOqI/ec7sFXCrtPfIxbej9 e5Gf6yrdTDly79r367G1n5nm1U/45c56fLHrrlcUGbc0Vpl84wmtvnbEXfHMmTSDJ/oXq+pvd lTeD/7R9eMTEtEOBWYmlOCPRUIu5qDgRACKLyB5pAgAA X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-14.tower-206.messagelabs.com!1485801042!43638321!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3689 invoked from network); 30 Jan 2017 18:30:42 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-14.tower-206.messagelabs.com with SMTP; 30 Jan 2017 18:30:42 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C7501595; Mon, 30 Jan 2017 10:30:42 -0800 (PST) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0B6633F24D; Mon, 30 Jan 2017 10:30:40 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Mon, 30 Jan 2017 18:31:30 +0000 Message-Id: <20170130183153.28566-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170130183153.28566-1-andre.przywara@arm.com> References: <20170130183153.28566-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Vijay Kilari Subject: [Xen-devel] [PATCH 05/28] ARM: GICv3 ITS: map ITS command buffer X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Instead of directly manipulating the tables in memory, an ITS driver sends commands via a ring buffer to the ITS h/w to create or alter the LPI mappings. Allocate memory for that buffer and tell the ITS about it to be able to send ITS commands. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3-its.c | 46 ++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/gic_v3_its.h | 6 ++++++ 2 files changed, 52 insertions(+) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index c31fef6..ad7cd2a 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -27,6 +27,8 @@ #include #include +#define ITS_CMD_QUEUE_SZ SZ_64K + #define BASER_ATTR_MASK \ ((0x3UL << GITS_BASER_SHAREABILITY_SHIFT) | \ (0x7UL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) | \ @@ -44,6 +46,45 @@ static uint64_t encode_phys_addr(paddr_t addr, int page_bits) return ret | (addr & GENMASK(51, 48)) >> (48 - 12); } +static void *its_map_cbaser(struct host_its *its) +{ + void __iomem *cbasereg = its->its_base + GITS_CBASER; + uint64_t reg, regc; + void *buffer; + paddr_t paddr; + + reg = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT; + reg |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT; + reg |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT; + + buffer = _xzalloc(ITS_CMD_QUEUE_SZ, PAGE_SIZE); + if ( !buffer ) + return NULL; + paddr = virt_to_maddr(buffer); + ASSERT(!(paddr & ~GENMASK(51, 12))); + + reg |= GITS_VALID_BIT | paddr; + reg |= ((ITS_CMD_QUEUE_SZ / PAGE_SIZE) - 1) & GITS_CBASER_SIZE_MASK; + writeq_relaxed(reg, cbasereg); + regc = readq_relaxed(cbasereg); + + /* If the ITS dropped shareability, drop cacheability as well. */ + if ( (regc & GITS_BASER_SHAREABILITY_MASK) == 0 ) + { + regc &= ~GITS_BASER_INNER_CACHEABILITY_MASK; + writeq_relaxed(regc, cbasereg); + } + + /* + * If the command queue memory is mapped as uncached, we need to flush + * it on every access. + */ + if ( !(regc & GITS_BASER_INNER_CACHEABILITY_MASK) ) + its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; + + return buffer; +} + #define PAGE_BITS(sz) ((sz) * 2 + PAGE_SHIFT) static int its_map_baser(void __iomem *basereg, uint64_t regc, int nr_items) @@ -150,6 +191,11 @@ int gicv3_its_init(struct host_its *hw_its) } } + hw_its->cmd_buf = its_map_cbaser(hw_its); + if ( !hw_its->cmd_buf ) + return -ENOMEM; + writeq_relaxed(0, hw_its->its_base + GITS_CWRITER); + return 0; } diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h index ed44bdb..ff5572f 100644 --- a/xen/include/asm-arm/gic_v3_its.h +++ b/xen/include/asm-arm/gic_v3_its.h @@ -65,9 +65,13 @@ #define GITS_BASER_OUTER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) #define GITS_BASER_INNER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT) +#define GITS_CBASER_SIZE_MASK 0xff + #ifndef __ASSEMBLY__ #include +#define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) + /* data structure for each hardware ITS */ struct host_its { struct list_head entry; @@ -75,6 +79,8 @@ struct host_its { paddr_t addr; paddr_t size; void __iomem *its_base; + void *cmd_buf; + unsigned int flags; }; extern struct list_head host_its_list;