From patchwork Tue Jan 31 11:07:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Liu X-Patchwork-Id: 9546923 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0474F6016C for ; Tue, 31 Jan 2017 11:10:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EBCDD2811E for ; Tue, 31 Jan 2017 11:10:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E0A9A28329; Tue, 31 Jan 2017 11:10:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 335E12811E for ; Tue, 31 Jan 2017 11:10:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cYWIS-0000aI-IV; Tue, 31 Jan 2017 11:08:24 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cYWIR-0000Xb-0N for xen-devel@lists.xenproject.org; Tue, 31 Jan 2017 11:08:23 +0000 Received: from [85.158.143.35] by server-10.bemta-6.messagelabs.com id CB/FE-13192-62070985; Tue, 31 Jan 2017 11:08:22 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmkeJIrShJLcpLzFFi42JxWrohUlelYEK EQedeA4vvWyYzOTB6HP5whSWAMYo1My8pvyKBNePTlH2sBU8CK9puzWVvYJxl18XIySEh4C/x cG87I4jNJqAs8bOzlw3EFhHQk2g68BwsziyQJ/F4VStYXFjARuLZ30YmEJtFQFXi0aNNYDavg IXEoc4vLBAz5SV2tV1k7WLk4OAUsJTY+SwXJCwEVHJuURcbhK0g0TH9GFSroMTJmU9YIFZJSB x88YJ5AiPvLCSpWUhSCxiZVjGqF6cWlaUW6RrpJRVlpmeU5CZm5ugaGpjp5aYWFyemp+YkJhX rJefnbmIEBg4DEOxgXPbX6RCjJAeTkijvZ+EJEUJ8SfkplRmJxRnxRaU5qcWHGGU4OJQkeKfl A+UEi1LTUyvSMnOAIQyTluDgURLhTcwDSvMWFyTmFmemQ6ROMSpKifNuA+kTAElklObBtcHi5 hKjrJQwLyPQIUI8BalFuZklqPKvGMU5GJWEee+CjOfJzCuBm/4KaDET0GL3V30gi0sSEVJSDY yCjjKXHar+fn09q/mAeex7m4rvrkKe2Z1HZ70O6ao/KLLUZb/jlFDxE82PqifcjxLUr9JdkXl JtHiTipLF1uzVgW9nBLFfVZvjvsyDV9F6y81tOTfrioUDYiWdLgjZ8bp7XhcKs9p002OFj8Ib o/l1AkHW3G/0z68ptL/Vdfym4VOJ/uzqF0osxRmJhlrMRcWJAOeWbcyWAgAA X-Env-Sender: prvs=1976b8d93=wei.liu2@citrix.com X-Msg-Ref: server-14.tower-21.messagelabs.com!1485860896!49548328!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 9.1.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 39212 invoked from network); 31 Jan 2017 11:08:19 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-14.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 31 Jan 2017 11:08:19 -0000 X-IronPort-AV: E=Sophos;i="5.33,314,1477958400"; d="scan'208";a="403086902" From: Wei Liu To: Xen-devel Date: Tue, 31 Jan 2017 11:07:59 +0000 Message-ID: <20170131110809.30001-3-wei.liu2@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170131110809.30001-1-wei.liu2@citrix.com> References: <20170131110809.30001-1-wei.liu2@citrix.com> MIME-Version: 1.0 Cc: Andrew Cooper , Wei Liu , Jan Beulich Subject: [Xen-devel] [PATCH v2 02/12] x86: extract macros to x86-defns.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP ... so that they can be used by userspace x86 instruction emulator test program and fuzzer as well. No functional change. Signed-off-by: Wei Liu --- Cc: Jan Beulich Cc: Andrew Cooper --- xen/include/asm-x86/processor.h | 97 +------------------------------------- xen/include/asm-x86/x86-defns.h | 100 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+), 95 deletions(-) create mode 100644 xen/include/asm-x86/x86-defns.h diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h index 4da9c193e0..ff0e51f3d5 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -16,6 +16,8 @@ #include #endif +#include "x86-defns.h" + /* * CPU vendor IDs */ @@ -25,101 +27,6 @@ #define X86_VENDOR_NUM 3 #define X86_VENDOR_UNKNOWN 0xff -/* - * EFLAGS bits - */ -#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ -#define X86_EFLAGS_MBS 0x00000002 /* Resvd bit */ -#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ -#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ -#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ -#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ -#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ -#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ -#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ -#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ -#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ -#define X86_EFLAGS_NT 0x00004000 /* Nested Task */ -#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ -#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ -#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ -#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ -#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ -#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ - -#define X86_EFLAGS_ARITH_MASK \ - (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ - X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) - -/* - * Intel CPU flags in CR0 - */ -#define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */ -#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */ -#define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */ -#define X86_CR0_TS 0x00000008 /* Task Switched (RW) */ -#define X86_CR0_ET 0x00000010 /* Extension type (RO) */ -#define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */ -#define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */ -#define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */ -#define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */ -#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */ -#define X86_CR0_PG 0x80000000 /* Paging (RW) */ - -/* - * Intel CPU features in CR4 - */ -#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ -#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ -#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ -#define X86_CR4_DE 0x00000008 /* enable debugging extensions */ -#define X86_CR4_PSE 0x00000010 /* enable page size extensions */ -#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ -#define X86_CR4_MCE 0x00000040 /* Machine check enable */ -#define X86_CR4_PGE 0x00000080 /* enable global pages */ -#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ -#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ -#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ -#define X86_CR4_VMXE 0x00002000 /* enable VMX */ -#define X86_CR4_SMXE 0x00004000 /* enable SMX */ -#define X86_CR4_FSGSBASE 0x00010000 /* enable {rd,wr}{fs,gs}base */ -#define X86_CR4_PCIDE 0x00020000 /* enable PCID */ -#define X86_CR4_OSXSAVE 0x00040000 /* enable XSAVE/XRSTOR */ -#define X86_CR4_SMEP 0x00100000 /* enable SMEP */ -#define X86_CR4_SMAP 0x00200000 /* enable SMAP */ -#define X86_CR4_PKE 0x00400000 /* enable PKE */ - -/* - * Trap/fault mnemonics. - */ -#define TRAP_divide_error 0 -#define TRAP_debug 1 -#define TRAP_nmi 2 -#define TRAP_int3 3 -#define TRAP_overflow 4 -#define TRAP_bounds 5 -#define TRAP_invalid_op 6 -#define TRAP_no_device 7 -#define TRAP_double_fault 8 -#define TRAP_copro_seg 9 -#define TRAP_invalid_tss 10 -#define TRAP_no_segment 11 -#define TRAP_stack_error 12 -#define TRAP_gp_fault 13 -#define TRAP_page_fault 14 -#define TRAP_spurious_int 15 -#define TRAP_copro_error 16 -#define TRAP_alignment_check 17 -#define TRAP_machine_check 18 -#define TRAP_simd_error 19 -#define TRAP_virtualisation 20 -#define TRAP_nr 32 - -#define TRAP_HAVE_EC \ - ((1u << TRAP_double_fault) | (1u << TRAP_invalid_tss) | \ - (1u << TRAP_no_segment) | (1u << TRAP_stack_error) | \ - (1u << TRAP_gp_fault) | (1u << TRAP_page_fault) | \ - (1u << TRAP_alignment_check)) /* Set for entry via SYSCALL. Informs return code to use SYSRETQ not IRETQ. */ /* NB. Same as VGCF_in_syscall. No bits in common with any other TRAP_ defn. */ diff --git a/xen/include/asm-x86/x86-defns.h b/xen/include/asm-x86/x86-defns.h new file mode 100644 index 0000000000..762938f222 --- /dev/null +++ b/xen/include/asm-x86/x86-defns.h @@ -0,0 +1,100 @@ +#ifndef __XEN_X86_DEFNS_H__ +#define __XEN_X86_DEFNS_H__ + +/* + * EFLAGS bits + */ +#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ +#define X86_EFLAGS_MBS 0x00000002 /* Resvd bit */ +#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ +#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ +#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ +#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ +#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ +#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ +#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ +#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ +#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ +#define X86_EFLAGS_NT 0x00004000 /* Nested Task */ +#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ +#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ +#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ +#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ +#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ +#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ + +#define X86_EFLAGS_ARITH_MASK \ + (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ + X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) + +/* + * Intel CPU flags in CR0 + */ +#define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */ +#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */ +#define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */ +#define X86_CR0_TS 0x00000008 /* Task Switched (RW) */ +#define X86_CR0_ET 0x00000010 /* Extension type (RO) */ +#define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */ +#define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */ +#define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */ +#define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */ +#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */ +#define X86_CR0_PG 0x80000000 /* Paging (RW) */ + +/* + * Intel CPU features in CR4 + */ +#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ +#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ +#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ +#define X86_CR4_DE 0x00000008 /* enable debugging extensions */ +#define X86_CR4_PSE 0x00000010 /* enable page size extensions */ +#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ +#define X86_CR4_MCE 0x00000040 /* Machine check enable */ +#define X86_CR4_PGE 0x00000080 /* enable global pages */ +#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ +#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ +#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ +#define X86_CR4_VMXE 0x00002000 /* enable VMX */ +#define X86_CR4_SMXE 0x00004000 /* enable SMX */ +#define X86_CR4_FSGSBASE 0x00010000 /* enable {rd,wr}{fs,gs}base */ +#define X86_CR4_PCIDE 0x00020000 /* enable PCID */ +#define X86_CR4_OSXSAVE 0x00040000 /* enable XSAVE/XRSTOR */ +#define X86_CR4_SMEP 0x00100000 /* enable SMEP */ +#define X86_CR4_SMAP 0x00200000 /* enable SMAP */ +#define X86_CR4_PKE 0x00400000 /* enable PKE */ + +/* + * Trap/fault mnemonics. + */ +#define TRAP_divide_error 0 +#define TRAP_debug 1 +#define TRAP_nmi 2 +#define TRAP_int3 3 +#define TRAP_overflow 4 +#define TRAP_bounds 5 +#define TRAP_invalid_op 6 +#define TRAP_no_device 7 +#define TRAP_double_fault 8 +#define TRAP_copro_seg 9 +#define TRAP_invalid_tss 10 +#define TRAP_no_segment 11 +#define TRAP_stack_error 12 +#define TRAP_gp_fault 13 +#define TRAP_page_fault 14 +#define TRAP_spurious_int 15 +#define TRAP_copro_error 16 +#define TRAP_alignment_check 17 +#define TRAP_machine_check 18 +#define TRAP_simd_error 19 +#define TRAP_virtualisation 20 +#define TRAP_nr 32 + +#define TRAP_HAVE_EC \ + ((1u << TRAP_double_fault) | (1u << TRAP_invalid_tss) | \ + (1u << TRAP_no_segment) | (1u << TRAP_stack_error) | \ + (1u << TRAP_gp_fault) | (1u << TRAP_page_fault) | \ + (1u << TRAP_alignment_check)) + +#endif /* __XEN_X86_DEFNS_H__ */