From patchwork Fri Feb 17 06:39:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 9578871 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 40C48600C5 for ; Fri, 17 Feb 2017 06:43:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 310092869B for ; Fri, 17 Feb 2017 06:43:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 25A6E286A8; Fri, 17 Feb 2017 06:43:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91DD22869B for ; Fri, 17 Feb 2017 06:43:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cecE7-0002lU-MM; Fri, 17 Feb 2017 06:41:07 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cecE5-0002iJ-T6 for xen-devel@lists.xen.org; Fri, 17 Feb 2017 06:41:05 +0000 Received: from [193.109.254.147] by server-2.bemta-6.messagelabs.com id 37/F7-31242-10B96A85; Fri, 17 Feb 2017 06:41:05 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRWlGSWpSXmKPExsVywNykWJdh9rI Ig/lLlC2WfFzM4sDocXT3b6YAxijWzLyk/IoE1oxPF1cwFjyWr+h5uISlgXG6RBcjF4eQwDRG iYn3X7N2MXJySAjwShxZNgPI5gCy/SRWPhWDqOlllLh+4ANYDZuAvsSKxwfBbBEBaYlrny8zg hQxC5xllFhyt4EJJCEsYCvxbMMaMJtFQFWi/W0LO4jNK2AnsXL5XmaIZfISF66eYgGxOYHifx 5+AKsRAup9/+ke8wRG3gWMDKsY1YtTi8pSi3RN9JKKMtMzSnITM3N0DQ3M9HJTi4sT01NzEpO K9ZLzczcxAsOBAQh2MHZf9j/EKMnBpCTKu2jasgghvqT8lMqMxOKM+KLSnNTiQ4wyHBxKErzc s4BygkWp6akVaZk5wMCESUtw8CiJ8HKApHmLCxJzizPTIVKnGBWlxHlvzARKCIAkMkrz4Npg0 XCJUVZKmJcR6BAhnoLUotzMElT5V4ziHIxKwrwXQKbwZOaVwE1/BbSYCWhxZ8RSkMUliQgpqQ bGfq99ImyzXZsXnmtY6aBz6Ms3DTlWU4mCo202POE81Utsj+d1Z/qaT5WKnabhNyn8mHVx9o6 DP5bGKvS/u/v79vnvTMqrTU4s4RHwnWSbdmtPzdQ/nyolas7caG1Ye6ySyyXtYX7u5z+B+1+3 /sxl7nOQfHj2S4HMPBl7H33RaGGTOe7Vi7cqsRRnJBpqMRcVJwIAyIlW9oECAAA= X-Env-Sender: haozhong.zhang@intel.com X-Msg-Ref: server-15.tower-27.messagelabs.com!1487313633!34675007!15 X-Originating-IP: [192.55.52.115] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 33906 invoked from network); 17 Feb 2017 06:41:04 -0000 Received: from mga14.intel.com (HELO mga14.intel.com) (192.55.52.115) by server-15.tower-27.messagelabs.com with DHE-RSA-AES256-GCM-SHA384 encrypted SMTP; 17 Feb 2017 06:41:04 -0000 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Feb 2017 22:41:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,171,1484035200"; d="scan'208";a="65781604" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.133]) by orsmga005.jf.intel.com with ESMTP; 16 Feb 2017 22:41:02 -0800 From: Haozhong Zhang To: xen-devel@lists.xen.org Date: Fri, 17 Feb 2017 14:39:32 +0800 Message-Id: <20170217063936.13208-16-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170217063936.13208-1-haozhong.zhang@intel.com> References: <20170217063936.13208-1-haozhong.zhang@intel.com> Cc: Haozhong Zhang , Christoph Egger , Andrew Cooper , Jan Beulich , Liu Jinsong Subject: [Xen-devel] [PATCH 15/19] x86/vmce: emulate MSR_IA32_MCG_EXT_CTL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then allow guest to read/write MSR_IA32_MCG_EXT_CTL. Signed-off-by: Haozhong Zhang --- Cc: Christoph Egger Cc: Liu Jinsong Cc: Jan Beulich Cc: Andrew Cooper --- xen/arch/x86/cpu/mcheck/vmce.c | 32 +++++++++++++++++++++++++++++++- xen/include/asm-x86/mce.h | 1 + xen/include/public/arch-x86/hvm/save.h | 2 ++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 456d6f3..1278839 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -90,6 +90,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt) v->arch.vmce.mcg_cap = ctxt->caps; v->arch.vmce.bank[0].mci_ctl2 = ctxt->mci_ctl2_bank0; v->arch.vmce.bank[1].mci_ctl2 = ctxt->mci_ctl2_bank1; + v->arch.vmce.lmce_enabled = ctxt->lmce_enabled; return 0; } @@ -190,6 +191,25 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) *val = ~0ULL; mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_CTL %#"PRIx64"\n", cur, *val); break; + case MSR_IA32_MCG_EXT_CTL: + /* + * If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, the LMCE and LOCK + * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen , so it + * does not need to check them here. + */ + if ( !(cur->arch.vmce.mcg_cap & MCG_LMCE_P) ) + { + ret = -1; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL, not supported\n", + cur); + } + else + { + *val = cur->arch.vmce.lmce_enabled ? MCG_EXT_CTL_LMCE_EN : 0; + mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", + cur, *val); + } + break; default: ret = mce_bank_msr(cur, msr) ? bank_mce_rdmsr(cur, msr, val) : 0; break; @@ -290,6 +310,15 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) */ mce_printk(MCE_VERBOSE, "MCE: %pv: MCG_CAP is r/o\n", cur); break; + case MSR_IA32_MCG_EXT_CTL: + if ( !(cur->arch.vmce.mcg_cap & MCG_LMCE_P) || + (val & ~MCG_EXT_CTL_LMCE_EN) ) + ret = -1; + else + cur->arch.vmce.lmce_enabled = !!(val & MCG_EXT_CTL_LMCE_EN); + mce_printk(MCE_VERBOSE, "MCE: %pv: wr MCG_EXT_CTL %"PRIx64"%s\n", + cur, val, (ret == -1) ? ", not supported" : ""); + break; default: ret = mce_bank_msr(cur, msr) ? bank_mce_wrmsr(cur, msr, val) : 0; break; @@ -308,7 +337,8 @@ static int vmce_save_vcpu_ctxt(struct domain *d, hvm_domain_context_t *h) struct hvm_vmce_vcpu ctxt = { .caps = v->arch.vmce.mcg_cap, .mci_ctl2_bank0 = v->arch.vmce.bank[0].mci_ctl2, - .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2 + .mci_ctl2_bank1 = v->arch.vmce.bank[1].mci_ctl2, + .lmce_enabled = v->arch.vmce.lmce_enabled, }; err = hvm_save_entry(VMCE_VCPU, v->vcpu_id, h, &ctxt); diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h index 6b827ef..525a9e8 100644 --- a/xen/include/asm-x86/mce.h +++ b/xen/include/asm-x86/mce.h @@ -29,6 +29,7 @@ struct vmce { uint64_t mcg_status; spinlock_t lock; struct vmce_bank bank[GUEST_MC_BANK_NUM]; + bool lmce_enabled; }; /* Guest vMCE MSRs virtualization */ diff --git a/xen/include/public/arch-x86/hvm/save.h b/xen/include/public/arch-x86/hvm/save.h index 8d73b51..2d62ec3 100644 --- a/xen/include/public/arch-x86/hvm/save.h +++ b/xen/include/public/arch-x86/hvm/save.h @@ -599,6 +599,8 @@ struct hvm_vmce_vcpu { uint64_t caps; uint64_t mci_ctl2_bank0; uint64_t mci_ctl2_bank1; + uint8_t lmce_enabled; + uint8_t _pad[7]; }; DECLARE_HVM_SAVE_TYPE(VMCE_VCPU, 18, struct hvm_vmce_vcpu);