From patchwork Thu Mar 16 11:20:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 9627917 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 87EF16048C for ; Thu, 16 Mar 2017 11:20:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C773285B5 for ; Thu, 16 Mar 2017 11:20:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7128A28604; Thu, 16 Mar 2017 11:20:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0ECEB285B5 for ; Thu, 16 Mar 2017 11:20:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coTQp-0007aR-GX; Thu, 16 Mar 2017 11:18:59 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1coTQn-0007V0-UJ for xen-devel@lists.xenproject.org; Thu, 16 Mar 2017 11:18:58 +0000 Received: from [193.109.254.147] by server-4.bemta-6.messagelabs.com id 71/21-25093-1A47AC85; Thu, 16 Mar 2017 11:18:57 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTXdeyak Ig4/fuSy+b5nM5MDocfjDFZYAxijWzLyk/IoE1ox1c86yF8yWq3j+eRdrA+NciS5GLg4hgc2M EvM2LWKFcJYzShxuPc/WxcjJwSagK7Hj5mtmEFtEIFRizs9HYDazQKXExQ/7wWqEBRwkNh25w gJiswioSvzYv4QJxOYVsJb423gNzJYQkJNoOH8frJdTwEai4+QesF4hoJrPRz+zT2DkXsDIsI pRozi1qCy1SNfQUi+pKDM9oyQ3MTNH19DATC83tbg4MT01JzGpWC85P3cTI9DDDECwg/HHsoB DjJIcTEqivCqCJyKE+JLyUyozEosz4otKc1KLDzHKcHAoSfByFwDlBItS01Mr0jJzgKEGk5bg 4FES4S0FSfMWFyTmFmemQ6ROMSpKifNWgSQEQBIZpXlwbbDwvsQoKyXMywh0iBBPQWpRbmYJq vwrRnEORiVhXjaQKTyZeSVw018BLWYCWpz48wjI4pJEhJRUA6OlzDrRqTUtDxcENS7kS/WJnD afLVOgfJfiGfUnC1fdW9Kzw9dvfWfA3reGFzdJ6acvetN/b7t63a9V6xn8jhzq4hDyVQvdcP7 bKR+HedqnyyzuG+p1/LWfNlOixHmeesm7tRee3Hnuey/A4rfzXfa4d8HRC6OjD+lWBrz2VlvQ 9/z14ZieVWlKLMUZiYZazEXFiQA93hscagIAAA== X-Env-Sender: andre.przywara@arm.com X-Msg-Ref: server-11.tower-27.messagelabs.com!1489663133!61604878!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.2.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 26694 invoked from network); 16 Mar 2017 11:18:53 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-11.tower-27.messagelabs.com with SMTP; 16 Mar 2017 11:18:53 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C68813D5; Thu, 16 Mar 2017 04:18:53 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 474D73F5C9; Thu, 16 Mar 2017 04:18:52 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 16 Mar 2017 11:20:07 +0000 Message-Id: <20170316112030.20419-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170316112030.20419-1-andre.przywara@arm.com> References: <20170316112030.20419-1-andre.przywara@arm.com> Cc: xen-devel@lists.xenproject.org, Shanker Donthineni , Vijay Kilari Subject: [Xen-devel] [PATCH v2 04/27] ARM: GICv3 ITS: map ITS command buffer X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Instead of directly manipulating the tables in memory, an ITS driver sends commands via a ring buffer in normal system memory to the ITS h/w to create or alter the LPI mappings. Allocate memory for that buffer and tell the ITS about it to be able to send ITS commands. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v3-its.c | 57 ++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/gic_v3_its.h | 6 +++++ 2 files changed, 63 insertions(+) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 9982fe9..e5601ed 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -20,10 +20,13 @@ #include #include +#include #include #include #include +#define ITS_CMD_QUEUE_SZ SZ_64K + LIST_HEAD(host_its_list); bool gicv3_its_host_has_its(void) @@ -56,6 +59,55 @@ static uint64_t encode_propbaser_phys_addr(paddr_t addr, unsigned int page_bits) return ret | ((addr & GENMASK(51, 48)) >> (48 - 12)); } +static void *its_map_cbaser(struct host_its *its) +{ + void __iomem *cbasereg = its->its_base + GITS_CBASER; + uint64_t reg; + void *buffer; + unsigned int order; + + reg = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT; + reg |= GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_SHIFT; + reg |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT; + + /* The ITS command buffer needs to be 64K aligned. */ + order = max(get_order_from_bytes(ITS_CMD_QUEUE_SZ), 16U - PAGE_SHIFT); + buffer = alloc_xenheap_pages(order, 0); + if ( !buffer ) + return NULL; + + if ( virt_to_maddr(buffer) & ~GENMASK(51, 12) ) + { + free_xenheap_pages(buffer, 0); + return NULL; + } + memset(buffer, 0, ITS_CMD_QUEUE_SZ); + + reg |= GITS_VALID_BIT | virt_to_maddr(buffer); + reg |= ((ITS_CMD_QUEUE_SZ / SZ_4K) - 1) & GITS_CBASER_SIZE_MASK; + writeq_relaxed(reg, cbasereg); + reg = readq_relaxed(cbasereg); + + /* If the ITS dropped shareability, drop cacheability as well. */ + if ( (reg & GITS_BASER_SHAREABILITY_MASK) == 0 ) + { + reg &= ~GITS_BASER_INNER_CACHEABILITY_MASK; + writeq_relaxed(reg, cbasereg); + } + + /* + * If the command queue memory is mapped as uncached, we need to flush + * it on every access. + */ + if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) + { + its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; + dprintk(XENLOG_WARNING, "using non-cacheable ITS command queue\n"); + } + + return buffer; +} + /* The ITS BASE registers work with page sizes of 4K, 16K or 64K. */ #define BASER_PAGE_BITS(sz) ((sz) * 2 + 12) @@ -175,6 +227,11 @@ static int gicv3_its_init_single_its(struct host_its *hw_its) } } + hw_its->cmd_buf = its_map_cbaser(hw_its); + if ( !hw_its->cmd_buf ) + return -ENOMEM; + writeq_relaxed(0, hw_its->its_base + GITS_CWRITER); + return 0; } diff --git a/xen/include/asm-arm/gic_v3_its.h b/xen/include/asm-arm/gic_v3_its.h index a6c0acc..d5facf0 100644 --- a/xen/include/asm-arm/gic_v3_its.h +++ b/xen/include/asm-arm/gic_v3_its.h @@ -74,8 +74,12 @@ #define GITS_BASER_OUTER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) #define GITS_BASER_INNER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT) +#define GITS_CBASER_SIZE_MASK 0xff + #include +#define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) + /* data structure for each hardware ITS */ struct host_its { struct list_head entry; @@ -83,6 +87,8 @@ struct host_its { paddr_t addr; paddr_t size; void __iomem *its_base; + void *cmd_buf; + unsigned int flags; };